公开(公告)号：US10068045B1

公开(公告)日：2018-09-04

申请号：US15374994

申请日：2016-12-09

Applicant: Xilinx, Inc.

Inventor： Sabyasachi Das ,  Chiwei Huang

IPC: G06F17/50

Abstract: A programmable logic design is generated for a programmable logic device (PLD) containing configurable logic blocks (CLBs) each having a plurality of multiplexers and look-up-table (LUT) circuits. A first subset of multiplexers are identified from the plurality of multiplexers based upon an analysis of design definitions for input signals of the plurality of multiplexers. The first subset of multiplexers are transformed into LUT logic. Configuration data is generated that is designed to be loaded into the PLD to configure the CLBs. The configuration data includes the LUT logic.

公开(公告)号：US09773083B1

公开(公告)日：2017-09-26

申请号：US15069598

申请日：2016-03-14

Applicant: Xilinx, Inc.

Inventor： Sabyasachi Das ,  Zhiyong Wang

IPC: G06F17/50

CPC classification number: G06F17/5077 ,  G06F17/5072 ,  G06F2217/84

Abstract: Aspects of processing a circuit design include synthesizing the circuit design and placing elements of the synthesized circuit design. After placing and before routing, respective delay values and slacks are determined. A first path having a most negative slack is determined and a first group of candidate paths is selected. The first group of candidate paths is a subset of critical paths of the circuit design, and the first group of candidate paths have delay values within a threshold range of delay values from the delay value of the first path. The first group of candidate paths are modified to reduce the respective delay values and a second group of candidate paths is selected. The second group of candidate paths have circuit structures that match selected circuit structures and are modified to reduce the respective delay values. A critical path having a most negative slack is iteratively selected and modified to reduce the respective delay value.

公开(公告)号：US09613173B1

公开(公告)日：2017-04-04

申请号：US14873072

申请日：2015-10-01

Applicant: Xilinx, Inc.

Inventor： Rajat Aggarwal ,  Zhiyong Wang ,  Ruibing Lu ,  Sabyasachi Das

IPC: G06F17/50

CPC classification number: G06F17/5054 ,  G06F17/5072 ,  G06F17/5077 ,  G06F17/5081 ,  G06F2217/78 ,  G06F2217/84

Abstract: A processor-implemented method is provided for placing and routing a circuit design. A first netlist is generated for the circuit design. Placement is performed for the first netlist on a target programmable integrated circuit (IC) to produce a first placed design. A set of optimizations are performed on the first placed design. The set of optimizations are recorded in an optimization history file. One or more optimizations specified in the optimization history file are performed on the first netlist to produce a second netlist that is different than the first netlist. Placement is performed for the second netlist on the target programmable IC to produce a second placed design that is different than the first placed design. Nets of the second placed design are routed to produce a placed and routed circuit design.

公开(公告)号：US10572621B1

公开(公告)日：2020-02-25

申请号：US16034242

申请日：2018-07-12

Applicant: Xilinx, Inc.

Inventor： Zhiyong Wang ,  Sabyasachi Das

IPC: G06F17/50

Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for performing physical synthesis with an overall placement process. One of the methods includes receiving an initial netlist of a circuit design for an IC. A global placement process is performed that assigns to some components in the initial netlist a respective initial location on the IC. One or more physical synthesis processes are performed to generate a modified netlist before assigning a final location to all components in the circuit design by an overall placement process. A subsequent placement process is performed to assign a final location on the IC to all components in the modified netlist.

公开(公告)号：US10565334B1

公开(公告)日：2020-02-18

申请号：US15849216

申请日：2017-12-20

Applicant: Xilinx, Inc.

Inventor： Ruibing Lu ,  Sabyasachi Das

IPC: G06F17/50 ,  G01R31/317 ,  G06F11/32

Abstract: Disclosed approaches for processing a circuit design include determining first slacks of cells, including a target cell, coupled to receive a clock signal through a first clock leaf. The first slacks are based on a current delay value specified for a first programmable delay circuit. The method predicts second slacks of the cells based on another delay value specified for the first programmable delay circuit, and then determines whether or not the second slacks indicate a degradation in timing relative to the first slacks. The current delay value of the first programmable delay circuit is adjusted to the other delay value in response to determining the second slacks indicates no degradation in timing. The target cell is reconnected to receive the clock signal from a second clock leaf having a second programmable delay circuit specified with the other delay value in response to determining the second slacks indicates degradation in timing.

公开(公告)号：US10540463B1

公开(公告)日：2020-01-21

申请号：US15895737

申请日：2018-02-13

Applicant: Xilinx, Inc.

Inventor： Maheshwar Chandrasekar ,  Sabyasachi Das

IPC: G06F17/50 ,  H03K19/177 ,  H01L21/822

Abstract: Disclosed approaches for processing a circuit design include identifying a driver and a load having a hold violation in the circuit design. The circuit design is targeted to an integrated circuit (IC) die. The method determines a first offset from a location on a perimeter of a rectangular region of the IC die having corners at locations of the driver and the load such that a length of a signal path from the driver through a first candidate location having placement coordinates that are outside the rectangular region and at the first offset from the location on the perimeter resolves the hold violation. The method determines availability of the first candidate location. In response to determining that the first candidate location is available, the method includes instantiating a delay circuit at the first candidate location and specifying connections that connect the delay circuit between the driver and the load.

公开(公告)号：US10242150B1

公开(公告)日：2019-03-26

申请号：US15175897

申请日：2016-06-07

Applicant: Xilinx, Inc.

Inventor： Sabyasachi Das ,  Xiaojian Yang ,  Niyati Shah ,  Govinda Keshavdas ,  Frederic Revenu

IPC: G06F17/50

Abstract: Circuit design implementation can include selecting a first and second load each having a control pin of a same type driven by a different driver, determining whether the driver of the first load matches the driver of the second load, and modifying the circuit design to drive the control pins of the first load and the second load using the driver of the first load. Circuit design implementation can include selecting a net having a driver and a plurality of loads exceeding a threshold, determining a selected module of the circuit design having a number of the plurality of loads of the net that meet a cloning criteria, and, in response, modifying the circuit design by creating a clone of the driver within the selected module and driving each load of the net within the selected module with the clone of the driver.

公开(公告)号：US09836568B1

公开(公告)日：2017-12-05

申请号：US15069524

申请日：2016-03-14

Applicant: Xilinx, Inc.

Inventor： Ilya K. Ganusov ,  Aaron Ng ,  Ronald E. Plyler ,  Sabyasachi Das ,  Frederic Revenu

IPC: G06F9/455 ,  G06F17/50

CPC classification number: G06F17/5072 ,  G06F17/5081

Abstract: Improving timing of a circuit design may include determining, using a processor, critical feed-forward paths of the circuit design, determining, using the processor, a sequential loop having a largest loop delay within the circuit design, and iteratively cutting, using the processor, the critical feed-forward paths and feed-forward paths parallel to the cut critical feed-forward paths until a stopping condition is met. The stopping condition may be determined according to the largest loop delay. The circuit design may be modified by inserting a register at each cut feed-forward path.

公开(公告)号：US09767247B1

公开(公告)日：2017-09-19

申请号：US14798269

申请日：2015-07-13

Applicant: Xilinx, Inc.

Inventor： Ruibing Lu ,  Sabyasachi Das

IPC: G06F17/00 ,  G06F17/50

CPC classification number: G06F17/5054 ,  G06F2217/84

Abstract: A method of circuit design may include identifying, using a processor, a timing critical path within a first look-up table structure in a circuit design and restructuring, using the processor, the first look-up table structure into a functionally equivalent second look-up table structure. The second look-up table structure may include fewer look-up tables serially coupled in the timing critical path than the first look-up table structure. The method may include placing, using the processor, the second look-up table structure and routing, using the processor, the second look-up table structure.

公开(公告)号：US09646126B1

公开(公告)日：2017-05-09

申请号：US14671920

申请日：2015-03-27

Applicant: Xilinx, Inc.

Inventor： Ruibing Lu ,  Zhiyong Wang ,  Aaron Ng ,  Sabyasachi Das

IPC: G06F9/455 ,  G06F17/50

CPC classification number: G06F17/5068 ,  G06F17/5031 ,  G06F17/5077 ,  G06F2217/84

Abstract: Post-routing processing of a circuit design may include determining, using a processor, a baseline delay for a path of a routed circuit design, comparing, using the processor, the baseline delay of the path with a timing constraint of the path, and selectively applying, according to the comparing, a structural netlist optimization to the path resulting in an optimized path using a processor.