公开(公告)号：US20080294776A1

公开(公告)日：2008-11-27

申请号：US11753468

申请日：2007-05-24

Applicant: Yi Ding

Inventor： Yi Ding

IPC: G06F15/173 ,  G06F9/44

CPC classification number: H04L67/16 ,  H04L67/02 ,  H04L69/18

Abstract: Techniques for supporting multiple service discovery protocols (SDPs) on a multi-functional peripheral (MFP) are provided. The MFP includes a plurality of SDP services, a plurality of SDP adapters, and a device service management system (DSMS). Each SDP service interfaces with one SDP adapter of the plurality of SDP adapters. Each SDP adapter interfaces with the DSMS. Each SDP adapter translates messages from its corresponding SDP service into a format the DSMS understands, and vice versa. The DSMS manages service metadata information about multiple services provided by the MFP. In response to a request, from a client, for metadata of one or more services provided by the MFP, a SDP service requests the metadata from its corresponding SDP adapter. The SDP adapter requests the metadata from the DSMS, which responds to the SDP adapter with the metadata. The SDP adapter sends the metadata to the SDP service, which sends the metadata to the client.

Abstract translation: 提供了在多功能外设（MFP）上支持多个服务发现协议（SDP）的技术。 MFP包括多个SDP服务，多个SDP适配器和设备服务管理系统（DSMS）。 每个SDP服务与多个SDP适配器的一个SDP适配器接口。 每个SDP适配器与DSMS接口。 每个SDP适配器将来自其对应的SDP服务的消息转换为DSMS所理解的格式，反之亦然。 DSMS管理由MFP提供的多个服务的服务元数据信息。 响应于来自客户端的针对由MFP提供的一个或多个服务的元数据的请求，SDP服务从其对应的SDP适配器请求元数据。 SDP适配器从DSMS请求元数据，DSMS使用元数据对SDP适配器进行响应。 SDP适配器将元数据发送到SDP服务，SDP服务将元数据发送给客户端。

公开(公告)号：US20080146014A1

公开(公告)日：2008-06-19

申请号：US11610948

申请日：2006-12-14

Applicant: Yi Ding

Inventor： Yi Ding

IPC: H01L21/44

CPC classification number: H01L21/76897 ,  H01L27/115 ,  H01L27/11521

Abstract: A semiconductor device comprises one or more self aligned contacts. The device may include one or more gate structures adjacent a first doped region. The device may comprise a first dielectric overlaying the gate structure and a first layer comprising silicon and overlaying a top of each said gate structure, the first layer being separated from each said conductive gate by the first dielectric. The first layer having an opening overlying the first doped region, and the first dielectric extends substantially down side portions of the opening. The device includes a first conductive contact having at least a portion extending into the opening, the contact electrically contacting the first doped region at a bottom region of the opening, the contact being insulated each conductive gate of each gate structure adjacent to the contact by the first dielectric.

Abstract translation: 半导体器件包括一个或多个自对准触点。 器件可以包括与第一掺杂区域相邻的一个或多个栅极结构。 该器件可以包括覆盖栅极结构的第一电介质和包括硅并且覆盖每个所述栅极结构的顶部的第一层，第一层通过第一电介质与每个所述导电栅极分离。 所述第一层具有覆盖所述第一掺杂区的开口，并且所述第一电介质基本上沿所述开口的下侧部分延伸。 该器件包括具有延伸到开口中的至少一部分的第一导电触点，该触点与开口底部区域处的第一掺杂区电接触，该触点与每个栅极结构的每个导电栅极相邻， 第一电介质。

公开(公告)号：US20080134423A1

公开(公告)日：2008-06-12

申请号：US11548335

申请日：2006-10-11

Applicant: Yi Ding

Inventor： Yi Ding

IPC: E03D9/08

CPC classification number: E03D9/08

Abstract: Disclosed is a bidet apparatus. The apparatus includes a second water supply source in addition to a source utilizing existing hot and cold supply lines. Dependent on the situation, these two sources can independently or cooperatively supply the water to a spray head mounted on the underside of a toilet seat.

Abstract translation: 公开了一种坐浴盆装置。 除了使用现有的冷热供应管线的源之外，该设备还包括第二供水源。 根据情况，这两个来源可以独立地或协同地将水供应到安装在马桶座下面的喷头上。

公开(公告)号：US20070264779A1

公开(公告)日：2007-11-15

申请号：US11828557

申请日：2007-07-26

Applicant: Chia-Shun Hsiao ,  Yi Ding

Inventor： Chia-Shun Hsiao ,  Yi Ding

IPC: H01L21/8247

CPC classification number: H01L27/11521 ,  H01L27/115 ,  H01L27/11519 ,  H01L29/42328 ,  H01L29/66825

Abstract: Dielectric regions (210) are formed on a semiconductor substrate between active areas of nonvolatile memory cells. The top portions of the dielectric region sidewalls are etched to recess the top portions laterally away from the active areas. Then a conductive layer is deposited to form the floating gates (410). The recessed portions of the dielectric sidewalls allow the floating gates to be wider at the top. The gate coupling ratio is increased as a result. Other features are also provided.

Abstract translation: 电介质区域（210）形成在非易失性存储单元的有源区域之间的半导体衬底上。 蚀刻电介质区域侧壁的顶部以将顶部部分横向远离有源区域。 然后沉积导电层以形成浮栅（410）。 电介质侧壁的凹陷部分允许浮动栅极在顶部较宽。 结果，门耦合比增大。 还提供其他功能。

公开(公告)号：US07274063B2

公开(公告)日：2007-09-25

申请号：US10964204

申请日：2004-10-12

Applicant: Yi Ding

Inventor： Yi Ding

IPC: H01L29/788

CPC classification number: H01L27/11526 ,  G11C16/0458 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11546 ,  H01L29/42328 ,  H01L29/7887

Abstract: In a nonvolatile memory cell having at least two floating gates, each floating gate (160) has an upward protruding portion. This portion can be formed as a spacer over a sidewall of the select gate (140). The spacer can be formed from a layer (160.2) deposited after the layer (160.1) which provides a lower portion of the floating gate. Alternatively, the upward protruding portion and the lower portion can be formed from the same layers or sub-layers all of which are present in both portions. The control gate (170) can be defined without photolithography. Other embodiments are also provided.

Abstract translation: 在具有至少两个浮动栅极的非易失性存储单元中，每个浮动栅极（160）具有向上突出部分。 该部分可以形成为在选择门（140）的侧壁上的间隔物。 隔离物可以由沉积在提供浮动栅极的下部的层（160.1）之后的层（160.2）形成。 或者，向上突出部分和下部分可以由相同的层或子层形成，所有这些层或子层都存在于两个部分中。 控制栅极（170）可以在没有光刻的情况下被定义。 还提供了其他实施例。

公开(公告)号：US07091091B2

公开(公告)日：2006-08-15

申请号：US10879782

申请日：2004-06-28

Applicant: Yi Ding

Inventor： Yi Ding

IPC: H01L21/336

CPC classification number: H01L27/11531 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11526

Abstract: A first dielectric (120) and a first floating gate layer (130.1) are formed on a semiconductor substrate (110). The first dielectric, the first floating gate layer, and the substrate are etched to form isolation trenches (150). The first dielectric (120) is etched to pull the first dielectric away from the trench edges (150E) and/or the edges of the first floating gate layer (130E). The trench edges and/or the edges of the first floating gate layer are then oxidized. The trenches are filled with a second dielectric (210.2), which is then etched laterally adjacent to the edges of the trench and the first floating gate layer. A second floating gate layer (130.2) is formed to extend into the regions which were occupied by the second dielectric before it was etched.

Abstract translation: 第一电介质（120）和第一浮栅（130.1）形成在半导体衬底（110）上。 蚀刻第一电介质，第一浮栅层和衬底以形成隔离沟槽（150）。 蚀刻第一电介质（120）以将第一电介质拉离第一浮动栅层（​​130E）的沟槽边缘（150E）和/或边缘。 然后，第一浮栅层的沟槽边缘和/或边缘被氧化。 沟槽填充有第二电介质（210.2），然后将其邻近蚀刻到沟槽和第一浮栅层的边缘。 第二浮栅层（130.2）被形成为延伸到被蚀刻之前由第二电介质占据的区域。

公开(公告)号：US20060108631A1

公开(公告)日：2006-05-25

申请号：US11321982

申请日：2005-12-28

Applicant: Yi Ding

Inventor： Yi Ding

IPC: H01L29/788 ,  H01L21/336

CPC classification number: H01L29/66825 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/7881

Abstract: In a nonvolatile memory, the select gates (144S) are formed from one conductive layer (e.g. polysilicon or polyside), and the wordlines (144) interconnecting the select gates are made from a different conductive layer (e.g. metal). The wordlines overlie an interlevel dielectric (310) formed over control gates (134). The dielectric thickness can be controlled to reduce the capacitance between the wordlines and the control gates. In some embodiments, the floating gates (120) are fabricated in a self-aligned manner using an isotropic etch of the floating gate layer.

Abstract translation: 在非易失性存储器中，选择栅极（144S）由一个导电层（例如多晶硅或多边形）形成，并且互连选择栅极的字线（144）由不同的导电层（例如金属）制成。 字线覆盖在控制栅极（134）上形成的层间电介质（310）。 可以控制电介质厚度以减小字线和控制门之间的电容。 在一些实施例中，使用浮动栅极层的各向同性蚀刻，以自对准的方式制造浮置栅极（120）。

公开(公告)号：US06962852B2

公开(公告)日：2005-11-08

申请号：US10631552

申请日：2003-07-30

Applicant: Yi Ding

Inventor： Yi Ding

IPC: H01L27/092 ,  H01L21/336 ,  H01L21/8238 ,  H01L21/8247 ,  H01L27/10 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792

CPC classification number: H01L27/115 ,  H01L27/11526 ,  H01L27/11546 ,  H01L29/42328 ,  H01L29/66825

Abstract: To fabricate a nonvolatile memory, a select gate (140) is formed over a semiconductor substrate. A dielectric (810, 1010, 1030) is formed over the select gate. A floating gate layer (160), e.g. doped polysilicon, is formed over the select gate. The floating gate layer is removed from over at least a portion of the select gate. A dielectric (1510), e.g., ONO, is formed over the floating gate layer, and a control gate layer (170) is formed over this dielectric. The control gate layer has an upward protrusion over the select gate. Then another layer (1710), e.g. silicon nitride, is formed on the control gate layer, but the protrusions of the control gate layer are exposed. The exposed portion of the control gate layer is etched selectively until the control gate layer is removed from over at least a portion of the select gate. Then another layer (1910) is formed on the exposed portion of the control gate layer. This is thermally grown silicon dioxide in some embodiments. Then the silicon nitride is removed. The control gate layer, the ONO, and the floating gate layer are etched selectively to the silicon dioxide to define the control and floating gates. Other embodiments are also provided.

Abstract translation: 为了制造非易失性存储器，在半导体衬底上形成选择栅极（140）。 在选择栅极上形成电介质（810,1010,1030）。 浮栅层（160），例如 掺杂多晶硅，形成在选择栅上。 浮选栅极层从选择栅极的至少一部分上方移除。 在浮置栅极层上形成电介质（例如ONO），并且在该电介质上形成控制栅极层（170）。 控制栅极层在选择栅极上具有向上的突起。 然后另一层（1710），例如 氮化硅形成在控制栅极层上，但是控制栅极层的突起被暴露。 选择性地蚀刻控制栅极层的暴露部分，直到控制栅极层从选择栅极的至少一部分上方去除。 然后在控制栅层的暴露部分上形成另一层（1910）。 在一些实施方案中，这是热生长的二氧化硅。 然后去除氮化硅。 控制栅极层，ONO和浮置栅极层被选择性地蚀刻到二氧化硅上以限定控制和浮动栅极。 还提供了其他实施例。

公开(公告)号：US20050202632A1

公开(公告)日：2005-09-15

申请号：US10797972

申请日：2004-03-10

Applicant: Yi Ding

Inventor： Yi Ding

IPC: H01L21/336 ,  H01L21/8238 ,  H01L21/8247 ,  H01L29/76

CPC classification number: H01L29/42344 ,  H01L21/28273 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11531

Abstract: In a nonvolatile memory, the select gates (144S) are formed from one conductive layer (e.g. polysilicon or polyside), and the wordlines (144) interconnecting the select gates are made from a different conductive layer (e.g. metal). The wordlines overlie an dielectric (302, 304, 310) formed over control gate lines (134). Each control gate line provides control gates for one column of the memory cells. The adjacent control gate lines for the adjacent memory columns are spaced from each other. The dielectric thickness can be controlled to reduce the capacitance between the wordlines and the control gates. In some embodiments, the floating gates (120) are fabricated in a self-aligned manner using an isotropic etch of the floating gate layer.

公开(公告)号：US20050199956A1

公开(公告)日：2005-09-15

申请号：US10798475

申请日：2004-03-10

Applicant: Yi Ding

Inventor： Yi Ding

IPC: H01L21/336 ,  H01L27/108 ,  H01L27/115 ,  H01L29/78 ,  H01L29/788

CPC classification number: H01L29/66825 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/7881

Abstract: In a nonvolatile memory, the select gates (144S) are formed from one conductive layer (e.g. polysilicon or polyside), and the wordlines (144) interconnecting the select gates are made from a different conductive layer (e.g. metal). The wordlines overlie an interlevel dielectric (310) formed over control gates (134). The dielectric thickness can be controlled to reduce the capacitance between the wordlines and the control gates. In some embodiments, the floating gates (120) are fabricated in a self-aligned manner using an isotropic etch of the floating gate layer.

Abstract translation: 在非易失性存储器中，选择栅极（144S）由一个导电层（例如多晶硅或多边形）形成，并且互连选择栅极的字线（144）由不同的导电层（例如金属）制成。 字线覆盖在控制栅极（134）上形成的层间电介质（310）。 可以控制电介质厚度以减小字线和控制门之间的电容。 在一些实施例中，使用浮动栅极层的各向同性蚀刻，以自对准的方式制造浮置栅极（120）。