公开(公告)号：US5725739A

公开(公告)日：1998-03-10

申请号：US677659

申请日：1996-07-08

Applicant: Yongjun Hu

Inventor： Yongjun Hu

IPC: C23C14/04 ,  C23C14/06 ,  C23C14/34 ,  C23C14/35 ,  H01L21/768

CPC classification number: C23C14/345 ,  C23C14/046 ,  C23C14/0682 ,  C23C14/35 ,  H01J37/3447 ,  H01L21/76877

Abstract: An alloy or composite is deposited in a recess feature of a semiconductor substrate by sputtering an alloy or composite target into a recess, to form a first layer of deposited material. The first layer of deposited material is resputtered at a low angle and low energy, to redeposit the first layer of deposited material onto the bottom of the recess as a second layer of deposited material having a different stoichiometry than that of the first deposited material. In a further embodiment, a sputtering chamber ambient is comprised of argon and nitrogen. In yet a further embodiment, the resputtering step is followed by deposition of at least one layer of material with a different stoichiometry than that of the second deposited layer, to form a "graded" stoichiometry of material deposited in the recess.

公开(公告)号：US20060263963A1

公开(公告)日：2006-11-23

申请号：US11495654

申请日：2006-07-28

Applicant: Yongjun Hu

Inventor： Yongjun Hu

IPC: H01L21/8238

CPC classification number: H01L21/823835 ,  H01L21/823842

Abstract: Complementary transistors and methods of forming the complementary transistors on a semiconductor assembly are described. The transistors can be formed from a metal silicon compound deficient of silicon bonding atoms on a dielectric material overlying a semiconductor substrate conductively doped for PMOS and NMOS regions. The metal silicon compound overlying the NMOS region is converted to a metal silicon nitride and the metal silicon compound overlying the PMOS region is converted to a metal silicide. NMOS transistor gate electrodes comprising metal silicon nitride and PMOS transistor gate electrodes comprising metal silicide can be formed.

公开(公告)号：US20050250275A1

公开(公告)日：2005-11-10

申请号：US11180288

申请日：2005-07-13

Applicant: Yongjun Hu

Inventor： Yongjun Hu

IPC: H01L21/8238

CPC classification number: H01L21/823835 ,  H01L21/823842

Abstract: Complementary transistors and methods of forming the complementary transistors on a semiconductor assembly are described. The transistors can be formed from a metal silicon compound deficient of silicon bonding atoms on a dielectric material overlying a semiconductor substrate conductively doped for PMOS and NMOS regions. The metal silicon compound overlying the NMOS region is converted to a metal silicon nitride and the metal silicon compound overlying the PMOS region is converted to a metal silicide. NMOS transistor gate electrodes comprising metal silicon nitride and PMOS transistor gate electrodes comprising metal silicide can be formed.

Abstract translation: 描述了在半导体组件上形成互补晶体管的互补晶体管和方法。 晶体管可以由覆盖在用于PMOS和NMOS区域导电掺杂的半导体衬底上的电介质材料上的缺陷硅键合原子的金属硅化合物形成。 覆盖在NMOS区域上的金属硅化合物被转换为金属氮化硅，并且覆盖PMOS区域的金属硅化合物转化为金属硅化物。 可以形成包括金属氮化硅的NMOS晶体管栅电极和包括金属硅化物的PMOS晶体管栅电极。

公开(公告)号：US20050000942A1

公开(公告)日：2005-01-06

申请号：US10881503

申请日：2004-06-29

Applicant: Whonchee Lee ,  Yongjun Hu

Inventor： Whonchee Lee ,  Yongjun Hu

IPC: C23F1/28 ,  H01L21/3213 ,  H01L21/768 ,  C23F1/00

CPC classification number: C23F1/28 ,  H01L21/32134 ,  H01L21/76895

Abstract: An etching method for use in integrated circuit fabrication includes providing a metal nitride layer on a substrate assembly, providing regions of cobalt silicide on first portions of the metal nitride layer, and providing regions of cobalt on second portions of the metal nitride layer. The regions of cobalt and the second portions of the metal nitride layer are removed with at least one solution including a mineral acid and a peroxide. The mineral acid may be selected from the group including HCl, H2SO4, H3PO4, HNO3, and dilute HF (preferably the mineral acid is HCl) and the peroxide may be hydrogen peroxide. Further, the removal of the regions of cobalt and the second portions of the metal nitride layer may include a one step process or a two step process. In the one step process, the regions of cobalt and the second portions of the metal nitride layer are removed with a single solution including the mineral acid and the peroxide. In the two step process, the regions of cobalt are removed with a first solution containing a mineral acid and a peroxide and the second portions of the metal nitride layer are removed with a second solution containing a peroxide. An etching composition including a mineral acid and a peroxide, preferably, HCl and hydrogen peroxide, is also described. The etching methods and compositions may be used in forming structures such as word lines, gate electrodes, local interconnects, etc.

Abstract translation: 用于集成电路制造的蚀刻方法包括在衬底组件上提供金属氮化物层，在金属氮化物层的第一部分上提供钴硅化物的区域，以及在金属氮化物层的第二部分上提供钴区域。 用至少一种包含无机酸和过氧化物的溶液除去钴的区域和金属氮化物层的第二部分。 无机酸可以选自HCl，H 2 SO 4，H 3 PO 4，HNO 3和稀HF（优选无机酸是HCl），并且过氧化物可以是过氧化氢。 此外，去除钴的区域和金属氮化物层的第二部分可以包括一步法或两步法。 在一步法中，用包含无机酸和过氧化物的单一溶液除去钴的区域和金属氮化物层的第二部分。 在两步法中，用含有无机酸和过氧化物的第一溶液除去钴的区域，并用含有过氧化物的第二溶液除去金属氮化物层的第二部分。 还描述了包含无机酸和过氧化物，优选HCl和过氧化氢的蚀刻组合物。 蚀刻方法和组合物可以用于形成诸如字线，栅电极，局部互连等的结构。

公开(公告)号：US06689685B2

公开(公告)日：2004-02-10

申请号：US10271259

申请日：2002-10-15

Applicant: Yongjun Hu

Inventor： Yongjun Hu

IPC: H01L2144

CPC classification number: H01L21/76856 ,  C23C14/0641 ,  H01L21/28052 ,  H01L21/2855 ,  H01L21/76841 ,  H01L21/76849 ,  H01L21/76864

Abstract: A process is disclosed for manufacturing a film that is smooth and has large nitride grains of a diffusion barrier material. Under the process, a nitride of the diffusion barrier material is deposited by physical vapor deposition in an environment of nitrogen. The nitrogen content of the environment is selected at an operating level such that nitride nuclei of the diffusion barrier material are evenly distributed. A grain growth step is then conducted in the nitrogen environment to grow a film of large nitride grains of the diffusion barrier material. Also disclosed is a stack structure suitable for MOS memory circuits incorporating a lightly nitrided refractory metal suicide diffusion barrier with a covering of a nitride of a diffusion barrier material. The stack structure is formed in accordance with the diffusion barrier material nitride film manufacturing process and exhibits high thermal stability, low resistivity, long range agglomeration blocking, and high surface smoothness.

Abstract translation: 公开了一种用于制造光滑并具有大的扩散阻挡材料的氮化物晶粒的膜的方法。 在该过程中，通过物理气相沉积在氮气环境中沉积扩散阻挡材料的氮化物。 选择环境氮含量，使得扩散阻挡材料的氮化物核均匀分布。 然后在氮环境中进行晶粒生长步骤，以生长扩散阻挡材料的大的氮化物晶粒的膜。 还公开了一种适合于MOS存储器电路的堆叠结构，该MOS存储器电路结合了具有覆盖扩散阻挡材料的氮化物的轻微氮化难熔金属硅化物扩散阻挡层。 堆叠结构根据扩散阻挡材料氮化物膜制造工艺形成，并且具有高热稳定性，低电阻率，远距离聚集阻挡和高表面光滑度。

公开(公告)号：US06680246B2

公开(公告)日：2004-01-20

申请号：US10271126

申请日：2002-10-15

Applicant: Yongjun Hu

Inventor： Yongjun Hu

IPC: H01L214763

CPC classification number: H01L21/76856 ,  C23C14/0641 ,  H01L21/28052 ,  H01L21/2855 ,  H01L21/76841 ,  H01L21/76849 ,  H01L21/76864

Abstract: A process is disclosed for manufacturing a film that is smooth and has large nitride grains of a diffusion barrier material. Under the process, a nitride of the diffusion barrier material is deposited by physical vapor deposition in an environment of nitrogen. The nitrogen content of the environment is selected at an operating level such that nitride nuclei of the diffusion barrier material are evenly distributed. A grain growth step is then conducted in the nitrogen environment to grow a film of large nitride grains of the diffusion barrier material. Also disclosed is a stack structure suitable for MOS memory circuits incorporating a lightly nitrided refractory metal silicide diffusion barrier with a covering of a nitride of a diffusion barrier material. The stack structure is formed in accordance with the diffusion barrier material nitride film manufacturing process and exhibits high thermal stability, low resistivity, long range agglomeration blocking, and high surface smoothness.

Abstract translation: 公开了一种用于制造光滑并具有大的扩散阻挡材料的氮化物晶粒的膜的方法。 在该过程中，通过物理气相沉积在氮气环境中沉积扩散阻挡材料的氮化物。 选择环境氮含量，使得扩散阻挡材料的氮化物核均匀分布。 然后在氮环境中进行晶粒生长步骤，以生长扩散阻挡材料的大的氮化物晶粒的膜。 还公开了一种适合于MOS存储器电路的堆叠结构，该MOS存储器电路结合了具有覆盖扩散阻挡材料的氮化物的轻度氮化难熔金属硅化物扩散阻挡层。 堆叠结构根据扩散阻挡材料氮化物膜制造工艺形成，并且具有高热稳定性，低电阻率，远距离聚集阻挡和高表面光滑度。

公开(公告)号：US06445045B1

公开(公告)日：2002-09-03

申请号：US09906464

申请日：2001-07-16

Applicant: Yongjun Hu

Inventor： Yongjun Hu

IPC: H01L2976

Abstract: Methods and apparatus for forming a conductor layer utilize an implanted matrix to form C54-titanium silicide. Word line stacks formed by the methods of the invention are used in sub-0.2 micron line width applications, interconnects, and silicided source/drain regions, among other applications, and have a lower resistivity and improved thermal stability.

公开(公告)号：US06436818B1

公开(公告)日：2002-08-20

申请号：US09455115

申请日：1999-12-06

Applicant: Yongjun Hu ,  Pai-Hung Pan ,  Er-Xuan Ping ,  Randhir P. S. Thakur ,  Scott DeBoer

Inventor： Yongjun Hu ,  Pai-Hung Pan ,  Er-Xuan Ping ,  Randhir P. S. Thakur ,  Scott DeBoer

IPC: H01L2976

CPC classification number: H01L21/28044 ,  H01L21/28052 ,  H01L29/4941

Abstract: Methods and apparatus for forming word line stacks comprise one, or a combination of the following: a silicon diffusion barrier layer, doped with oxygen or nitrogen, coupled between a bottom silicon layer and a conductor layer; an amorphous silicon diffusion barrier coupled between a polysilicon layer and a conductor layer; a thin nitride layer coupled between a bottom silicon layer and a titanium silicide conductor layer, and a bottom silicon layer coupled to a conductor layer, which comprises C54-titanium silicide. Word line stacks formed by the methods of the invention are used in sub-0.25 micron line width applications and have a lower resistivity and improved thermal stability.

Abstract translation: 用于形成字线堆叠的方法和装置包括以下的一个或组合：掺杂有氧或氮的硅扩散阻挡层，耦合在底部硅层和导体层之间; 耦合在多晶硅层和导体层之间的非晶硅扩散势垒; 耦合在底部硅层和硅化钛导体层之间的薄氮化物层和耦合到导体层的底部硅层，其包含C54-硅酸钛。 通过本发明的方法形成的字线叠层用于0.25μm以下的线宽应用，并具有较低的电阻率和改善的热稳定性。

公开(公告)号：US06262458B1

公开(公告)日：2001-07-17

申请号：US08802884

申请日：1997-02-19

Applicant: Yongjun Hu

Inventor： Yongjun Hu

IPC: H01L2976

CPC classification number: H01L21/28052 ,  Y10S977/869 ,  Y10S977/89

Abstract: Methods and apparatus for forming a conductor layer utilize an implanted matrix to form C54-titanium silicide. Word line stacks formed by the methods of the invention are used in sub-0.25 micron line width applications, interconnects, and silicided source/drain regions, among other applications, and have a lower resistivity and improved thermal stability.

Abstract translation: 用于形成导体层的方法和装置利用注入的基体来形成C54-硅化钛。 通过本发明的方法形成的字线叠层在其他应用中用于0.25微米以下的线宽应用，互连和硅化源/漏区，并具有较低的电阻率和改善的热稳定性。

公开(公告)号：US6096640A

公开(公告)日：2000-08-01

申请号：US54328

申请日：1998-04-02

Applicant: Yongjun Hu

Inventor： Yongjun Hu

IPC: H01L21/28 ,  H01L29/49 ,  H01L21/44

CPC classification number: H01L21/28061 ,  H01L29/4941 ,  Y10S257/915

Abstract: Disclosed is a gate electrode stack structure that uses a refractory metal silicon nitride layer as a diffusion barrier. The gate electrode stack has several layers, including a gate oxide layer over the semiconductor substrate, a polysilicon layer over the gate oxide layer, and the diffusion barrier between the polysilicon layer and a layer of electrically conductive material above. The diffusion barrier, which is preferably composed of a substantially amorphous refractory metal silicon nitride such as tungsten silicon nitride, does not oxidize when an oxidation process is applied to the gate electrode stack. Moreover, the diffusion barrier substantially prevents diffusion of the electrically conductive material into the polysilicon during heating processes. The refractory metal silicon nitride maintains a bulk resistivity less than 2,000 microhm-cm, thereby preserving satisfactory conductivity in the gate electrode stack. A process for forming the gate electrode stack and diffusion barrier is also disclosed.

Abstract translation: 公开了使用难熔金属氮化硅层作为扩散阻挡层的栅电极堆叠结构。 栅极电极堆叠具有数层，包括半导体衬底上的栅极氧化物层，栅极氧化物层上的多晶硅层，以及多晶硅层与上述导电材料层之间的扩散阻挡层。 扩散阻挡层优选由基本上无定形的难熔金属氮化硅如氮化硅钨构成，当氧化工艺施加到栅电极堆时，其不会氧化。 此外，扩散阻挡层基本上防止在加热过程中导电材料扩散到多晶硅中。 难熔金属氮化硅保持体电阻率小于2,000微欧姆 - 厘米，从而保持栅电极堆叠中令人满意的导电性。 还公开了一种用于形成栅极电极堆叠和扩散阻挡层的工艺。