公开(公告)号：US20090258479A1

公开(公告)日：2009-10-15

申请号：US12488095

申请日：2009-06-19

申请人： Tamae TAKANO ,  Shunpei YAMAZAKI

发明人： Tamae TAKANO ,  Shunpei YAMAZAKI

IPC分类号： H01L21/28 ,  H01L21/22

CPC分类号： H01L27/12 ,  H01L21/84 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524

摘要： A nonvolatile semiconductor memory device is provided in such a manner that a semiconductor layer is formed over a substrate, a charge accumulating layer is formed over the semiconductor layer with a first insulating layer interposed therebetween, and a gate electrode is provided over the charge accumulating layer with a second insulating layer interposed therebetween. The semiconductor layer includes a channel formation region provided in a region overlapping with the gate electrode, a first impurity region for forming a source region or drain region, which is provided to be adjacent to the channel formation region, and a second impurity region provided to be adjacent to the channel formation region and the first impurity region. A conductivity type of the first impurity region is different from that of the second impurity region.

摘要翻译： 以半导体层形成在基板上的方式设置非易失性半导体存储元件，在半导体层上形成电荷累积层，其间插入有第一绝缘层，在电荷累积层之上设置栅电极 其间插入有第二绝缘层。 半导体层包括设置在与栅电极重叠的区域中的沟道形成区域，用于形成与沟道形成区域相邻的源极区域或漏极区域的第一杂质区域和设置成与沟道形成区域相邻的第二杂质区域 与沟道形成区域和第一杂质区域相邻。 第一杂质区的导电类型与第二杂质区不同。

公开(公告)号：US20090098720A1

公开(公告)日：2009-04-16

申请号：US12334589

申请日：2008-12-15

申请人： Atsuo ISOBE ,  Satoshi MURAKAMI ,  Tamae TAKANO ,  Shunpei YAMAZAKI

发明人： Atsuo ISOBE ,  Satoshi MURAKAMI ,  Tamae TAKANO ,  Shunpei YAMAZAKI

IPC分类号： H01L21/28 ,  H01L21/31

CPC分类号： H01L29/66757 ,  H01L27/12 ,  H01L27/1248 ,  H01L29/42384

摘要： A manufacturing method of a semiconductor device of the present invention includes the steps of forming a first insulating film over a substrate, forming a semiconductor film over the first insulating film, oxidizing or nitriding the semiconductor film by conducting a plasma treatment to the semiconductor film under a condition of an electron density of 1×1011 cm−3 or more and 1×1013 cm−3 or less and an electron temperature of 0.5 eV or more and 1.5 eV or less, using a high frequency wave, forming a second insulating film to cover the semiconductor film, forming a gate electrode over the second insulating film, forming a third insulating film to cover the gate electrode, and forming a conductive film over the third insulating film.

摘要翻译： 本发明的半导体器件的制造方法包括以下步骤：在衬底上形成第一绝缘膜，在第一绝缘膜上形成半导体膜，通过对半导体膜进行等离子体处理来对半导体膜进行氧化或氮化 使用高频波，电子密度为1×10 11 cm -3以上且1×10 13 cm -3以下，电子温度为0.5eV以上且1.5eV以下的条件，形成覆盖半导体的第2绝缘膜 在所述第二绝缘膜上形成栅电极，形成第三绝缘膜以覆盖所述栅电极，以及在所述第三绝缘膜上形成导电膜。

公开(公告)号：US20110031561A1

公开(公告)日：2011-02-10

申请号：US12909393

申请日：2010-10-21

申请人： Tamae TAKANO ,  Atsuo ISOBE

发明人： Tamae TAKANO ,  Atsuo ISOBE

IPC分类号： H01L29/786

CPC分类号： H01L29/78606 ,  H01L27/1214 ,  H01L27/1266 ,  H01L27/13 ,  H01L29/0603 ,  H01L29/78609 ,  H01L29/78636

摘要： The present invention provides a semiconductor device which suppresses a short circuit and a leakage current between a semiconductor film and a gate electrode generated by a break or thin thickness of a gate insulating film in an end portion of a channel region of the semiconductor film, and the manufacturing method of the semiconductor device. Plural thin film transistors which each have semiconductor film provided over a substrate continuously, conductive films provided over the semiconductor film through a gate insulating film, source and drain regions provided in the semiconductor film which are not overlapped with the conductive films, and channel regions provided in the semiconductor film existing under the conductive films and between the source and drain regions. And impurity regions provided in the semiconductor film which is not overlapped with the conductive film and provided adjacent to the source and drain regions. Further, the conductive films are provided over the channel regions and regions of the semiconductor film which are provided adjacent to the channel regions.

摘要翻译： 本发明提供一种半导体器件，其抑制由半导体膜的沟道区域的端部中的栅极绝缘膜的断裂或薄的厚度产生的半导体膜和栅电极之间的短路和漏电流，以及 半导体器件的制造方法。 连续地设置在基板上的半导体膜的多个薄膜晶体管，通过栅极绝缘膜设置在半导体膜上的导电膜，设置在半导体膜中的不与导电膜重叠的源区和漏区，以及设置的沟道区 在存在于导电膜之下以及源极和漏极区之间的半导体膜中。 以及设置在半导体膜中的不与导电膜重叠并且设置在源极和漏极区附近的杂质区。 此外，导电膜设置在与沟道区相邻设置的半导体膜的沟道区域和区域之上。

公开(公告)号：US20100187524A1

公开(公告)日：2010-07-29

申请号：US12751300

申请日：2010-03-31

申请人： Atsuo ISOBE ,  Tamae TAKANO ,  Yasuyuki ARAI ,  Fumiko TERASAWA

发明人： Atsuo ISOBE ,  Tamae TAKANO ,  Yasuyuki ARAI ,  Fumiko TERASAWA

IPC分类号： H01L29/786 ,  H01L29/12 ,  H01L29/788

CPC分类号： H01L27/12 ,  H01L21/84 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524

摘要： A manufacturing method of a semiconductor device of the present invention includes the steps of forming a stacked body in which a semiconductor film, a gate insulating film, and a first conductive film are sequentially stacked over a substrate; selectively removing the stacked body to form a plurality of island-shaped stacked bodies; forming an insulating film to cover the plurality of island-shaped stacked bodies; removing a part of the insulating film to expose a surface of the first conductive film, such that a surface of the first conductive film almost coextensive with a height of the insulating film; forming a second conductive film over the first conductive film and a left part of the insulating film; forming a resist over the second conductive film; selectively removing the first conductive film and the second conductive film using the resist as a mask.

摘要翻译： 本发明的半导体器件的制造方法包括以下步骤：在衬底上依次层叠有半导体膜，栅极绝缘膜和第一导电膜的层叠体; 选择性地去除层叠体以形成多个岛状堆叠体; 形成绝缘膜以覆盖所述多个岛状堆叠体; 去除绝缘膜的一部分以暴露第一导电膜的表面，使得第一导电膜的表面几乎与绝缘膜的高度共同延伸; 在所述第一导电膜和所述绝缘膜的左部分上形成第二导电膜; 在所述第二导电膜上形成抗蚀剂; 使用抗蚀剂作为掩模选择性地去除第一导电膜和第二导电膜。

公开(公告)号：US20100038618A1

公开(公告)日：2010-02-18

申请号：US12578650

申请日：2009-10-14

申请人： Tamae TAKANO ,  Kiyoshi KATO ,  Hideaki KUWABARA

发明人： Tamae TAKANO ,  Kiyoshi KATO ,  Hideaki KUWABARA

IPC分类号： H01L45/00

CPC分类号： H01L27/12 ,  B82Y10/00 ,  G11C11/5664 ,  G11C13/0014 ,  H01L27/1214 ,  H01L27/1255 ,  H01L27/1266 ,  H01L27/13 ,  H01L51/0595

摘要： The invention provides a novel memory for which process technology is relatively simple and which can store multivalued information by a small number of elements. A part of a shape of the first electrode in the first storage element is made different from a shape of the first electrode in the second storage element, and thereby voltage values which change electric resistance between the first electrode and the second electrode are varied, so that one memory cell stores multivalued information over one bit. By partially processing the first electrode, storage capacity per unit area can be increased.

摘要翻译： 本发明提供了一种新颖的存储器，其工艺技术相对简单，并且可以通过少量元件存储多值信息。 使第一存储元件中的第一电极的形状的一部分与第二存储元件中的第一电极的形状不同，从而改变第一电极和第二电极之间改变电阻的电压值，因此 一个存储单元存储超过一位的多值信息。 通过部分地处理第一电极，可以增加每单位面积的存储容量。