公开(公告)号：US5088063A

公开(公告)日：1992-02-11

申请号：US532338

申请日：1990-06-05

申请人： Yoshio Matsuda ,  Kazutami Arimoto ,  Tsukasa Ooishi ,  Masaki Tsukude ,  Kazuyasu Fujishima

发明人： Yoshio Matsuda ,  Kazutami Arimoto ,  Tsukasa Ooishi ,  Masaki Tsukude ,  Kazuyasu Fujishima

IPC分类号： G11C11/401 ,  G11C11/407 ,  G11C29/00 ,  G11C29/30 ,  G11C29/34

CPC分类号： G11C29/30

摘要： In a memory cell array of a semiconductor memory device, a plurality of detection circuits (14, 15, 20) are provided in correspondence with a plurality of columns. An output line (L) is provided in common to the detection circuits (14, 15, 20). The output line (L) is provided with plural junction points (nl to nn) to which detection results from the detection circuits (14, 15, 20) are separately applied. Dividing transistors (Tl to Tn) are provided between the junction points (nl to nn). During testing, the work lines (WLl to WLn) are selected sequentially. Test results for the memory cells (MC1 to MC4 ) connected to the selected word line are outputted at the corresponding junction points (nl to nn), respectively. Simultaneously, a dividing transistor corresponding to the selected word line is rendered non-conductive, the remaining dividing transistors being rendered conductive. As a result, the output line (L) is divided into two parts at a portion of the non-conductive transistor. Detection results outputted to the respective divided parts of the output line (L) are monitored and a portion at which a detection result is changed in each divided part is found out.

摘要翻译： 在半导体存储器件的存储单元阵列中，与多个列对应地提供多个检测电路（14,15,20）。 输出线（L）与检测电路（14,15,20）共同设置。 输出线（L）设置有分别施加有来自检测电路（14,15,20）的检测结果的多个结点（n1至nn）。 分接晶体管（T1至Tn）设置在连接点（nl至nn）之间。 在测试期间，依次选择工作线（WL1至WLn）。 连接到所选字线的存储单元（MC1至MC4）的测试结果分别在对应的连接点（nl至nn）输出。 同时，与所选字线对应的分割晶体管不导通，剩余的分割晶体管导通。 结果，输出线（L）在非导电晶体管的一部分被分成两部分。 检测输出到输出线（L）的分割部分的检测结果，并且求出检测结果在各分割部分发生变化的部分。

公开(公告)号：US5060230A

公开(公告)日：1991-10-22

申请号：US400899

申请日：1989-08-30

申请人： Kazutami Arimoto ,  Kazuyasu Fujishima ,  Yoshio Matsuda ,  Tsukasa Ooishi ,  Masaki Tsukude

发明人： Kazutami Arimoto ,  Kazuyasu Fujishima ,  Yoshio Matsuda ,  Tsukasa Ooishi ,  Masaki Tsukude

IPC分类号： G06F11/267 ,  G11C29/00 ,  G11C29/12 ,  G11C29/34

CPC分类号： G11C29/78 ,  G11C29/12 ,  G11C29/34 ,  G06F11/267

摘要： An apparatus for parallel testing of a semiconductor memory with arbitrary data patterns and capable of being integrated on the memory chip. The semiconductor memory test device in a preferred embodiment is compatible with hierarchical data bus lines including an input/output line pair (I/O, I/O), a plurality of sub-input/output line pairs (SIO1SIO1; SIO2, SIO2) and a plurality of bit line pairs (BL1, BL1; BL6, BL6). A plurality of comparators (50) and a plurality of registers (60) are provided corresponding to a plurality of sub-input/output line pairs (SIO1, SIO2; SIO2, SIO2). The plurality of registers (50) which also functions as intermediated output amplifiers can hold random data applied through the input/output line pair (I/O, I/O). The plurality of comparators (60) is provided to determine whether or not data read out onto a plurality of sub-input/output line pairs (SIO1, SIO1; SIO2, SIO2) from a row of memory cells (MC1, MC2) corresponding to a single word line (WL) match respective data held in the plurality of registers (60).

摘要翻译： 一种用于并行测试具有任意数据模式并能够集成在存储器芯片上的半导体存储器的装置。 优选实施例中的半导体存储器测试装置与包括输入/​​输出线对（I / O，I / O），多个子输入/输出线对（SIO1 + L，SIO1; SIO2，SIO2）和多个位线对（BL1，BL1; BL6，BL6）。 对应于多个子输入/输出线对（SIO1，SIO2; SIO2，SIO2）提供多个比较器（50）和多个寄存器（60）。 也可以用作中间输出放大器的多个寄存器（50）可以保存通过输入/输出线对（I / O，I / O）施加的随机数据。 多个比较器（60）被提供以确定从对应于存储单元（MC1，MC2）的一行的多个子输入/输出线对（SIO1，SIO1; SIO2，SIO2） 单个字线（WL）匹配保存在多个寄存器（60）中的相应数据。

公开(公告)号：US5315548A

公开(公告)日：1994-05-24

申请号：US900368

申请日：1992-06-18

申请人： Tsukasa Ooishi ,  Kazutami Arimoto ,  Hideto Hidaka ,  Masanori Hayashikoshi ,  Shinji Kawai ,  Mikio Asakura ,  Masaki Tsukude ,  Katsuhiro Suma ,  Shigeki Tomishima ,  Kazuyasu Fujishima

发明人： Tsukasa Ooishi ,  Kazutami Arimoto ,  Hideto Hidaka ,  Masanori Hayashikoshi ,  Shinji Kawai ,  Mikio Asakura ,  Masaki Tsukude ,  Katsuhiro Suma ,  Shigeki Tomishima ,  Kazuyasu Fujishima

IPC分类号： G11C11/407 ,  G11C7/10 ,  G11C8/12 ,  G11C11/401 ,  G11C11/41 ,  H01L21/8242 ,  H01L27/108 ,  G11C8/00 ,  G11C7/00

CPC分类号： G11C8/12 ,  G11C7/10

摘要： Column address A0-A11 is once predecoded by a first predecoder PD1, a second predecoder PD2, and a CDE buffer CDB and then applied to a column decoder CD. Column decoder CD selectively drives one of a plurality of column selecting lines CSL on the basis of the applied predecoded signals. This causes corresponding bit lines in respective memory cell arrays MCA1-MCA4 to be simultaneously selected. Column decoder CD includes a plurality of column drivers corresponding to the plurality of column selecting lines, and the column drivers are divided into a plurality of groups. The predecoded signals applied from second predecoder PD2 and CDE buffer CDB to column decoder CD are generated independently for respective groups, and signal lines for them are also distributed to respective groups. This causes the length of wiring of each predecoded signal line to be shortened.

摘要翻译： 列地址A0-A11由第一预解码器PD1，第二预解码器PD2和CDE缓冲器CDB预先解码，然后应用于列解码器CD。 列解码器CD基于所应用的预解码信号选择性地驱动多个列选择线CSL中的一个。 这使得相应的存储单元阵列MCA1-MCA4中的相应位线被同时选择。 列解码器CD包括对应于多个列选择线的多个列驱动器，列驱动器被分成多个组。 从第二预解码器PD2和CDE缓冲器CDB施加到列解码器CD的预解码信号针对各个组独立地生成，并且它们的信号线也被分配给各个组。 这导致每个预解码信号线的布线长度被缩短。

公开(公告)号：US06414883B2

公开(公告)日：2002-07-02

申请号：US09860795

申请日：2001-05-21

申请人： Hideto Hidaka ,  Mikio Asakura ,  Kazuyasu Fujishima ,  Tsukasa Ooishi ,  Kazutami Arimoto ,  Shigeki Tomishima ,  Masaki Tsukude

发明人： Hideto Hidaka ,  Mikio Asakura ,  Kazuyasu Fujishima ,  Tsukasa Ooishi ,  Kazutami Arimoto ,  Shigeki Tomishima ,  Masaki Tsukude

IPC分类号： G11C700

CPC分类号： G11C11/4085 ,  G11C5/14 ,  G11C5/147 ,  G11C7/062 ,  G11C7/067 ,  G11C7/12 ,  G11C7/14 ,  G11C8/08 ,  G11C11/4074 ,  G11C11/4091

摘要： Drains of first and second transistors are connected to a low level line of an internal circuitry such as a sense amplifier related to determination of a potential in a memory cell. The first transistor has its gate diode-connected to a sense drive line and its source grounded. The second transistor receives at its gate an internally generated signal, and its source is grounded. In the standby state, the potential of the sense drive line is set higher than low level of said word lines by the threshold voltage Vthn of the first transistor and used as dummy GND potential Vss′, and in the active state, the second transistor is rendered conductive so as to prevent floating of the sense drive line from the dummy GND potential Vss′.

公开(公告)号：USRE36089E

公开(公告)日：1999-02-09

申请号：US652008

申请日：1996-05-23

申请人： Tsukasa Ooishi ,  Kazutami Arimoto ,  Hideto Hidaka ,  Masanori Hayashikoshi ,  Shinji Kawai ,  Mikio Asakura ,  Masaki Tsukude ,  Katsuhiro Suma ,  Shigeki Tomishima ,  Kazuyasu Fujishima

发明人： Tsukasa Ooishi ,  Kazutami Arimoto ,  Hideto Hidaka ,  Masanori Hayashikoshi ,  Shinji Kawai ,  Mikio Asakura ,  Masaki Tsukude ,  Katsuhiro Suma ,  Shigeki Tomishima ,  Kazuyasu Fujishima

IPC分类号： G11C11/407 ,  G11C7/10 ,  G11C8/12 ,  G11C11/401 ,  G11C11/41 ,  H01L21/8242 ,  H01L27/108 ,  G11C7/00

CPC分类号： G11C8/12 ,  G11C7/10

摘要： Column address A0-A11 is once predecoded by a first predecoder PD1, a second predecoder PD2, and a CDE buffer CDB and then applied to a column decoder CD. Column decoder CD selectively drives one of a plurality of column selecting lines CSL on the basis of the applied predecoded signals. This causes corresponding bit lines in respective memory cell arrays MCA1-MCA4 to be simultaneously selected. Column decoder CD includes a plurality of column drivers corresponding to the plurality of column selecting lines, and the column drivers are divided into a plurality of groups. The predecoded signals applied from second predecoder PD2 and CDE buffer CDB to column decoder CD are generated independently for respective groups, and signal lines for them are also distributed to respective groups. This causes the length of wiring of each predecoded signal line to be shortened.

摘要翻译： 列地址A0-A11由第一预解码器PD1，第二预解码器PD2和CDE缓冲器CDB预先解码，然后应用于列解码器CD。 列解码器CD基于所应用的预解码信号选择性地驱动多个列选择线CSL中的一个。 这使得相应的存储单元阵列MCA1-MCA4中的相应位线被同时选择。 列解码器CD包括对应于多个列选择线的多个列驱动器，列驱动器被分成多个组。 从第二预解码器PD2和CDE缓冲器CDB施加到列解码器CD的预解码信号针对各个组独立地生成，并且它们的信号线也被分配给各个组。 这导致每个预解码信号线的布线长度被缩短。

公开(公告)号：US06859403B2

公开(公告)日：2005-02-22

申请号：US10815798

申请日：2004-04-02

申请人： Hideto Hidaka ,  Mikio Asakura ,  Kazuyasu Fujishima ,  Tsukasa Ooishi ,  Kazutami Arimoto ,  Shigeki Tomishima ,  Masaki Tsukude

发明人： Hideto Hidaka ,  Mikio Asakura ,  Kazuyasu Fujishima ,  Tsukasa Ooishi ,  Kazutami Arimoto ,  Shigeki Tomishima ,  Masaki Tsukude

IPC分类号： G11C11/407 ,  G11C5/14 ,  G11C7/06 ,  G11C7/12 ,  G11C7/14 ,  G11C8/08 ,  G11C11/401 ,  G11C11/4074 ,  G11C11/408 ,  G11C11/409 ,  G11C11/4091 ,  H01L21/8242 ,  H01L27/108

CPC分类号： G11C11/4085 ,  G11C5/14 ,  G11C5/147 ,  G11C7/062 ,  G11C7/067 ,  G11C7/12 ,  G11C7/14 ,  G11C8/08 ,  G11C11/4074 ,  G11C11/4091

摘要： Drains of first and second transistors are connected to a low level line of an internal circuitry such as a sense amplifier related to determination of a potential in a memory cell. The first transistor has its gate diode-connected to a sense drive line and its source grounded. The second transistor receives at its gate an internally generated signal, and its source is grounded. In the standby state, the potential of the sense drive line is set higher than low level of said word lines by the threshold voltage Vthn of the first transistor and used as dummy GND potential Vss′, and in the active state, the second transistor is rendered conductive so as to prevent floating of the sense drive line from the dummy GND potential Vss′.

摘要翻译： 第一和第二晶体管的漏极连接到诸如与确定存储器单元中的电位相关的读出放大器的内部电路的低电平线。 第一个晶体管的栅极二极管连接到感测驱动线，其源极接地。 第二晶体管在其栅极处接收内部产生的信号，其源极接地。 在待机状态下，将感测驱动线的电位设定为比第一晶体管的阈值电压Vthn高于所述字线的低电平，并将其用作虚设GND电位Vss'，而在激活状态下，第二晶体管为 导通，以防止感测驱动线从虚拟GND电位Vss'浮起。

公开(公告)号：US06272055B1

公开(公告)日：2001-08-07

申请号：US09168962

申请日：1998-10-09

申请人： Hideto Hidaka ,  Mikio Asakura ,  Kazuyasu Fujishima ,  Tsukasa Ooishi ,  Kazutami Arimoto ,  Shigeki Tomishima ,  Masaki Tsukude

发明人： Hideto Hidaka ,  Mikio Asakura ,  Kazuyasu Fujishima ,  Tsukasa Ooishi ,  Kazutami Arimoto ,  Shigeki Tomishima ,  Masaki Tsukude

IPC分类号： G11C700

CPC分类号： G11C11/4085 ,  G11C5/14 ,  G11C5/147 ,  G11C7/062 ,  G11C7/067 ,  G11C7/12 ,  G11C7/14 ,  G11C8/08 ,  G11C11/4074 ,  G11C11/4091

摘要： Drains of first and second transistors are connected to a low level line of an internal circuitry such as a sense amplifier related to determination of a potential in a memory cell. The first transistor has its gate diode-connected to a sense drive line and its source grounded. The second transistor receives at its gate an internally generated signal, and its source is grounded. In the standby state, the potential of the sense drive line is set higher than low level of said word lines by the threshold voltage Vthn of the first transistor and used as dummy GND potential Vss′, and in the active state, the second transistor is rendered conductive so as to prevent floating of the sense drive line from the dummy GND potential Vss′.

公开(公告)号：US5943273A

公开(公告)日：1999-08-24

申请号：US899143

申请日：1997-07-23

申请人： Hideto Hidaka ,  Mikio Asakura ,  Kazuyasu Fujishima ,  Tsukasa Ooishi ,  Kazutami Arimoto ,  Shigeki Tomishima ,  Masaki Tsukude

发明人： Hideto Hidaka ,  Mikio Asakura ,  Kazuyasu Fujishima ,  Tsukasa Ooishi ,  Kazutami Arimoto ,  Shigeki Tomishima ,  Masaki Tsukude

IPC分类号： G11C11/407 ,  G11C5/14 ,  G11C7/06 ,  G11C7/12 ,  G11C7/14 ,  G11C8/08 ,  G11C11/401 ,  G11C11/4074 ,  G11C11/408 ,  G11C11/409 ,  G11C11/4091 ,  H01L21/8242 ,  H01L27/108 ,  G11C7/00

CPC分类号： G11C11/4085 ,  G11C11/4074 ,  G11C11/4091 ,  G11C5/14 ,  G11C5/147 ,  G11C7/062 ,  G11C7/067 ,  G11C7/12 ,  G11C7/14 ,  G11C8/08

摘要： Drains of first and second transistors are connected to a low level line of an internal circuitry such as a sense amplifier related to determination of a potential in a memory cell. The first transistor has its gate diode-connected to a sense drive line and its source grounded. The second transistor receives at its gate an internally generated signal, and its source is grounded. In the standby state, the potential of the sense drive line is set higher than low level of said word lines by the threshold voltage Vthn of the first transistor and used as dummy GND potential Vss', and in the active state, the second transistor is rendered conductive so as to prevent floating of the sense drive line from the dummy GND potential Vss'.

公开(公告)号：US5687123A

公开(公告)日：1997-11-11

申请号：US312968

申请日：1994-09-30

申请人： Hideto Hidaka ,  Mikio Asakura ,  Kazuyasu Fujishima ,  Tsukasa Ooishi ,  Kazutami Arimoto ,  Shigeki Tomishima ,  Masaki Tsukude

发明人： Hideto Hidaka ,  Mikio Asakura ,  Kazuyasu Fujishima ,  Tsukasa Ooishi ,  Kazutami Arimoto ,  Shigeki Tomishima ,  Masaki Tsukude

IPC分类号： G11C11/407 ,  G11C5/14 ,  G11C7/06 ,  G11C7/12 ,  G11C7/14 ,  G11C8/08 ,  G11C11/401 ,  G11C11/4074 ,  G11C11/408 ,  G11C11/409 ,  G11C11/4091 ,  H01L21/8242 ,  H01L27/108 ,  G11C7/00

CPC分类号： G11C11/4085 ,  G11C11/4074 ,  G11C11/4091 ,  G11C5/14 ,  G11C5/147 ,  G11C7/062 ,  G11C7/067 ,  G11C7/12 ,  G11C7/14 ,  G11C8/08

摘要： Drains of first and second transistors are connected to a low level line of an internal circuitry such as a sense amplifier related to determination of a potential in a memory cell. The first transistor has its gate diode-connected to a sense drive line and its source grounded. The second transistor receives at its gate an internally generated signal, and its source is grounded. In the standby state, the potential of the sense drive line is set higher than low level of said word lines by the threshold voltage Vthn of the first transistor and used as dummy GND potential Vss', and in the active state, the second transistor is rendered conductive so as to prevent floating of the sense drive line from the dummy GND potential Vss'.

摘要翻译： 第一和第二晶体管的漏极连接到诸如与确定存储器单元中的电位相关的读出放大器的内部电路的低电平线。 第一个晶体管的栅极二极管连接到感测驱动线，其源极接地。 第二晶体管在其栅极处接收内部产生的信号，其源极接地。 在待机状态下，将感测驱动线的电位设定为比第一晶体管的阈值电压Vthn高于所述字线的低电平，并将其用作虚设GND电位Vss'，而在激活状态下，第二晶体管为 导通，以防止感测驱动线从虚拟GND电位Vss'浮起。

公开(公告)号：US5136543A

公开(公告)日：1992-08-04

申请号：US741208

申请日：1991-07-31

申请人： Yoshio Matsuda ,  Kazuyasu Fujishima ,  Kazutami Arimoto ,  Masaki Tsukude ,  Tsukasa Oishi

发明人： Yoshio Matsuda ,  Kazuyasu Fujishima ,  Kazutami Arimoto ,  Masaki Tsukude ,  Tsukasa Oishi

IPC分类号： G11C7/10

CPC分类号： G11C7/1006

摘要： A semiconductor memory device comprises a plurality of bit line pairs and an input/output line pair. Each bit line pair comprises first and second bit lines supplied with complementary data, and the input/output line pair comprises first and second input/output lines supplied with complementary data. A switching circuit is provided on each bit line pair. Each switching circuit, in response to a control signal according to an address signal, respectively couples the first and the second bit lines to the first and the second input/output lines, or inversely, respectively couples the first and the second bit lines to the second and the first input/output lines.

摘要翻译： 半导体存储器件包括多个位线对和一个输入/输出线对。 每个位线对包括提供有互补数据的第一和第二位线，并且输入/输出线对包括提供有互补数据的第一和第二输入/输出线。 在每个位线对上提供开关电路。 每个开关电路响应于根据地址信号的控制信号分别将第一和第二位线耦合到第一和第二输入/输出线，或者相反地将第一和第二位线耦合到 第二个和第一个输入/输出线。