公开(公告)号：US5315548A

公开(公告)日：1994-05-24

申请号：US900368

申请日：1992-06-18

申请人： Tsukasa Ooishi ,  Kazutami Arimoto ,  Hideto Hidaka ,  Masanori Hayashikoshi ,  Shinji Kawai ,  Mikio Asakura ,  Masaki Tsukude ,  Katsuhiro Suma ,  Shigeki Tomishima ,  Kazuyasu Fujishima

发明人： Tsukasa Ooishi ,  Kazutami Arimoto ,  Hideto Hidaka ,  Masanori Hayashikoshi ,  Shinji Kawai ,  Mikio Asakura ,  Masaki Tsukude ,  Katsuhiro Suma ,  Shigeki Tomishima ,  Kazuyasu Fujishima

IPC分类号： G11C11/407 ,  G11C7/10 ,  G11C8/12 ,  G11C11/401 ,  G11C11/41 ,  H01L21/8242 ,  H01L27/108 ,  G11C8/00 ,  G11C7/00

CPC分类号： G11C8/12 ,  G11C7/10

摘要： Column address A0-A11 is once predecoded by a first predecoder PD1, a second predecoder PD2, and a CDE buffer CDB and then applied to a column decoder CD. Column decoder CD selectively drives one of a plurality of column selecting lines CSL on the basis of the applied predecoded signals. This causes corresponding bit lines in respective memory cell arrays MCA1-MCA4 to be simultaneously selected. Column decoder CD includes a plurality of column drivers corresponding to the plurality of column selecting lines, and the column drivers are divided into a plurality of groups. The predecoded signals applied from second predecoder PD2 and CDE buffer CDB to column decoder CD are generated independently for respective groups, and signal lines for them are also distributed to respective groups. This causes the length of wiring of each predecoded signal line to be shortened.

摘要翻译： 列地址A0-A11由第一预解码器PD1，第二预解码器PD2和CDE缓冲器CDB预先解码，然后应用于列解码器CD。 列解码器CD基于所应用的预解码信号选择性地驱动多个列选择线CSL中的一个。 这使得相应的存储单元阵列MCA1-MCA4中的相应位线被同时选择。 列解码器CD包括对应于多个列选择线的多个列驱动器，列驱动器被分成多个组。 从第二预解码器PD2和CDE缓冲器CDB施加到列解码器CD的预解码信号针对各个组独立地生成，并且它们的信号线也被分配给各个组。 这导致每个预解码信号线的布线长度被缩短。

公开(公告)号：USRE36089E

公开(公告)日：1999-02-09

申请号：US652008

申请日：1996-05-23

申请人： Tsukasa Ooishi ,  Kazutami Arimoto ,  Hideto Hidaka ,  Masanori Hayashikoshi ,  Shinji Kawai ,  Mikio Asakura ,  Masaki Tsukude ,  Katsuhiro Suma ,  Shigeki Tomishima ,  Kazuyasu Fujishima

发明人： Tsukasa Ooishi ,  Kazutami Arimoto ,  Hideto Hidaka ,  Masanori Hayashikoshi ,  Shinji Kawai ,  Mikio Asakura ,  Masaki Tsukude ,  Katsuhiro Suma ,  Shigeki Tomishima ,  Kazuyasu Fujishima

IPC分类号： G11C11/407 ,  G11C7/10 ,  G11C8/12 ,  G11C11/401 ,  G11C11/41 ,  H01L21/8242 ,  H01L27/108 ,  G11C7/00

CPC分类号： G11C8/12 ,  G11C7/10

摘要： Column address A0-A11 is once predecoded by a first predecoder PD1, a second predecoder PD2, and a CDE buffer CDB and then applied to a column decoder CD. Column decoder CD selectively drives one of a plurality of column selecting lines CSL on the basis of the applied predecoded signals. This causes corresponding bit lines in respective memory cell arrays MCA1-MCA4 to be simultaneously selected. Column decoder CD includes a plurality of column drivers corresponding to the plurality of column selecting lines, and the column drivers are divided into a plurality of groups. The predecoded signals applied from second predecoder PD2 and CDE buffer CDB to column decoder CD are generated independently for respective groups, and signal lines for them are also distributed to respective groups. This causes the length of wiring of each predecoded signal line to be shortened.

摘要翻译： 列地址A0-A11由第一预解码器PD1，第二预解码器PD2和CDE缓冲器CDB预先解码，然后应用于列解码器CD。 列解码器CD基于所应用的预解码信号选择性地驱动多个列选择线CSL中的一个。 这使得相应的存储单元阵列MCA1-MCA4中的相应位线被同时选择。 列解码器CD包括对应于多个列选择线的多个列驱动器，列驱动器被分成多个组。 从第二预解码器PD2和CDE缓冲器CDB施加到列解码器CD的预解码信号针对各个组独立地生成，并且它们的信号线也被分配给各个组。 这导致每个预解码信号线的布线长度被缩短。

公开(公告)号：US06414883B2

公开(公告)日：2002-07-02

申请号：US09860795

申请日：2001-05-21

申请人： Hideto Hidaka ,  Mikio Asakura ,  Kazuyasu Fujishima ,  Tsukasa Ooishi ,  Kazutami Arimoto ,  Shigeki Tomishima ,  Masaki Tsukude

发明人： Hideto Hidaka ,  Mikio Asakura ,  Kazuyasu Fujishima ,  Tsukasa Ooishi ,  Kazutami Arimoto ,  Shigeki Tomishima ,  Masaki Tsukude

IPC分类号： G11C700

CPC分类号： G11C11/4085 ,  G11C5/14 ,  G11C5/147 ,  G11C7/062 ,  G11C7/067 ,  G11C7/12 ,  G11C7/14 ,  G11C8/08 ,  G11C11/4074 ,  G11C11/4091

摘要： Drains of first and second transistors are connected to a low level line of an internal circuitry such as a sense amplifier related to determination of a potential in a memory cell. The first transistor has its gate diode-connected to a sense drive line and its source grounded. The second transistor receives at its gate an internally generated signal, and its source is grounded. In the standby state, the potential of the sense drive line is set higher than low level of said word lines by the threshold voltage Vthn of the first transistor and used as dummy GND potential Vss′, and in the active state, the second transistor is rendered conductive so as to prevent floating of the sense drive line from the dummy GND potential Vss′.

公开(公告)号：US06859403B2

公开(公告)日：2005-02-22

申请号：US10815798

申请日：2004-04-02

申请人： Hideto Hidaka ,  Mikio Asakura ,  Kazuyasu Fujishima ,  Tsukasa Ooishi ,  Kazutami Arimoto ,  Shigeki Tomishima ,  Masaki Tsukude

发明人： Hideto Hidaka ,  Mikio Asakura ,  Kazuyasu Fujishima ,  Tsukasa Ooishi ,  Kazutami Arimoto ,  Shigeki Tomishima ,  Masaki Tsukude

IPC分类号： G11C11/407 ,  G11C5/14 ,  G11C7/06 ,  G11C7/12 ,  G11C7/14 ,  G11C8/08 ,  G11C11/401 ,  G11C11/4074 ,  G11C11/408 ,  G11C11/409 ,  G11C11/4091 ,  H01L21/8242 ,  H01L27/108

CPC分类号： G11C11/4085 ,  G11C5/14 ,  G11C5/147 ,  G11C7/062 ,  G11C7/067 ,  G11C7/12 ,  G11C7/14 ,  G11C8/08 ,  G11C11/4074 ,  G11C11/4091

摘要： Drains of first and second transistors are connected to a low level line of an internal circuitry such as a sense amplifier related to determination of a potential in a memory cell. The first transistor has its gate diode-connected to a sense drive line and its source grounded. The second transistor receives at its gate an internally generated signal, and its source is grounded. In the standby state, the potential of the sense drive line is set higher than low level of said word lines by the threshold voltage Vthn of the first transistor and used as dummy GND potential Vss′, and in the active state, the second transistor is rendered conductive so as to prevent floating of the sense drive line from the dummy GND potential Vss′.

摘要翻译： 第一和第二晶体管的漏极连接到诸如与确定存储器单元中的电位相关的读出放大器的内部电路的低电平线。 第一个晶体管的栅极二极管连接到感测驱动线，其源极接地。 第二晶体管在其栅极处接收内部产生的信号，其源极接地。 在待机状态下，将感测驱动线的电位设定为比第一晶体管的阈值电压Vthn高于所述字线的低电平，并将其用作虚设GND电位Vss'，而在激活状态下，第二晶体管为 导通，以防止感测驱动线从虚拟GND电位Vss'浮起。

公开(公告)号：US06272055B1

公开(公告)日：2001-08-07

申请号：US09168962

申请日：1998-10-09

申请人： Hideto Hidaka ,  Mikio Asakura ,  Kazuyasu Fujishima ,  Tsukasa Ooishi ,  Kazutami Arimoto ,  Shigeki Tomishima ,  Masaki Tsukude

发明人： Hideto Hidaka ,  Mikio Asakura ,  Kazuyasu Fujishima ,  Tsukasa Ooishi ,  Kazutami Arimoto ,  Shigeki Tomishima ,  Masaki Tsukude

IPC分类号： G11C700

CPC分类号： G11C11/4085 ,  G11C5/14 ,  G11C5/147 ,  G11C7/062 ,  G11C7/067 ,  G11C7/12 ,  G11C7/14 ,  G11C8/08 ,  G11C11/4074 ,  G11C11/4091

摘要： Drains of first and second transistors are connected to a low level line of an internal circuitry such as a sense amplifier related to determination of a potential in a memory cell. The first transistor has its gate diode-connected to a sense drive line and its source grounded. The second transistor receives at its gate an internally generated signal, and its source is grounded. In the standby state, the potential of the sense drive line is set higher than low level of said word lines by the threshold voltage Vthn of the first transistor and used as dummy GND potential Vss′, and in the active state, the second transistor is rendered conductive so as to prevent floating of the sense drive line from the dummy GND potential Vss′.

公开(公告)号：US5943273A

公开(公告)日：1999-08-24

申请号：US899143

申请日：1997-07-23

申请人： Hideto Hidaka ,  Mikio Asakura ,  Kazuyasu Fujishima ,  Tsukasa Ooishi ,  Kazutami Arimoto ,  Shigeki Tomishima ,  Masaki Tsukude

发明人： Hideto Hidaka ,  Mikio Asakura ,  Kazuyasu Fujishima ,  Tsukasa Ooishi ,  Kazutami Arimoto ,  Shigeki Tomishima ,  Masaki Tsukude

IPC分类号： G11C11/407 ,  G11C5/14 ,  G11C7/06 ,  G11C7/12 ,  G11C7/14 ,  G11C8/08 ,  G11C11/401 ,  G11C11/4074 ,  G11C11/408 ,  G11C11/409 ,  G11C11/4091 ,  H01L21/8242 ,  H01L27/108 ,  G11C7/00

CPC分类号： G11C11/4085 ,  G11C11/4074 ,  G11C11/4091 ,  G11C5/14 ,  G11C5/147 ,  G11C7/062 ,  G11C7/067 ,  G11C7/12 ,  G11C7/14 ,  G11C8/08

摘要： Drains of first and second transistors are connected to a low level line of an internal circuitry such as a sense amplifier related to determination of a potential in a memory cell. The first transistor has its gate diode-connected to a sense drive line and its source grounded. The second transistor receives at its gate an internally generated signal, and its source is grounded. In the standby state, the potential of the sense drive line is set higher than low level of said word lines by the threshold voltage Vthn of the first transistor and used as dummy GND potential Vss', and in the active state, the second transistor is rendered conductive so as to prevent floating of the sense drive line from the dummy GND potential Vss'.

公开(公告)号：US5687123A

公开(公告)日：1997-11-11

申请号：US312968

申请日：1994-09-30

申请人： Hideto Hidaka ,  Mikio Asakura ,  Kazuyasu Fujishima ,  Tsukasa Ooishi ,  Kazutami Arimoto ,  Shigeki Tomishima ,  Masaki Tsukude

发明人： Hideto Hidaka ,  Mikio Asakura ,  Kazuyasu Fujishima ,  Tsukasa Ooishi ,  Kazutami Arimoto ,  Shigeki Tomishima ,  Masaki Tsukude

IPC分类号： G11C11/407 ,  G11C5/14 ,  G11C7/06 ,  G11C7/12 ,  G11C7/14 ,  G11C8/08 ,  G11C11/401 ,  G11C11/4074 ,  G11C11/408 ,  G11C11/409 ,  G11C11/4091 ,  H01L21/8242 ,  H01L27/108 ,  G11C7/00

CPC分类号： G11C11/4085 ,  G11C11/4074 ,  G11C11/4091 ,  G11C5/14 ,  G11C5/147 ,  G11C7/062 ,  G11C7/067 ,  G11C7/12 ,  G11C7/14 ,  G11C8/08

摘要： Drains of first and second transistors are connected to a low level line of an internal circuitry such as a sense amplifier related to determination of a potential in a memory cell. The first transistor has its gate diode-connected to a sense drive line and its source grounded. The second transistor receives at its gate an internally generated signal, and its source is grounded. In the standby state, the potential of the sense drive line is set higher than low level of said word lines by the threshold voltage Vthn of the first transistor and used as dummy GND potential Vss', and in the active state, the second transistor is rendered conductive so as to prevent floating of the sense drive line from the dummy GND potential Vss'.

摘要翻译： 第一和第二晶体管的漏极连接到诸如与确定存储器单元中的电位相关的读出放大器的内部电路的低电平线。 第一个晶体管的栅极二极管连接到感测驱动线，其源极接地。 第二晶体管在其栅极处接收内部产生的信号，其源极接地。 在待机状态下，将感测驱动线的电位设定为比第一晶体管的阈值电压Vthn高于所述字线的低电平，并将其用作虚设GND电位Vss'，而在激活状态下，第二晶体管为 导通，以防止感测驱动线从虚拟GND电位Vss'浮起。

公开(公告)号：US5249155A

公开(公告)日：1993-09-28

申请号：US819208

申请日：1992-01-10

申请人： Kazutami Arimoto ,  Hideto Hidaka ,  Mikio Asakura ,  Masanori Hayashikoshi ,  Masaki Tsukude ,  Shinji Kawai ,  Tsukasa Ooishi

发明人： Kazutami Arimoto ,  Hideto Hidaka ,  Mikio Asakura ,  Masanori Hayashikoshi ,  Masaki Tsukude ,  Shinji Kawai ,  Tsukasa Ooishi

IPC分类号： H01L21/8234 ,  G05F1/46 ,  G11C5/14 ,  G11C11/401 ,  G11C11/403 ,  G11C11/407 ,  G11C11/409 ,  H01L21/822 ,  H01L21/8244 ,  H01L27/04 ,  H01L27/06 ,  H01L27/10 ,  H01L27/11 ,  H03K17/30

CPC分类号： H03K17/302 ,  G05F1/465 ,  G11C5/147 ,  H01L2924/0002

摘要： An n channel driver circuit comprised of an N channel MOS transistor is provided in parallel to a driver circuit comprised of a P channel MOS transistor. Normally, n channel driver circuit supplies an internal supply voltage, to activate driver circuit only at the time of current peak. Thus, an insufficient capability of n.sup.- channel driver circuit to supply current is supplemented.

摘要翻译： 由N沟道MOS晶体管构成的n沟道驱动电路与由P沟道MOS晶体管构成的驱动电路并联设置。 通常，n通道驱动电路提供内部电源电压，仅在当前峰值时激活驱动电路。 因此，补充了n沟道驱动电路不足以提供电流的能力。

公开(公告)号：US5894440A

公开(公告)日：1999-04-13

申请号：US189276

申请日：1994-01-31

申请人： Masaki Tsukude ,  Kazutami Arimoto ,  Kazuyasu Fujishima ,  Yoshio Matsuda ,  Tsukasa Ooishi

发明人： Masaki Tsukude ,  Kazutami Arimoto ,  Kazuyasu Fujishima ,  Yoshio Matsuda ,  Tsukasa Ooishi

IPC分类号： G11C11/401 ,  G11C7/06 ,  G11C7/10 ,  G11C11/409

CPC分类号： G11C7/06 ,  G11C7/1006 ,  G11C7/1039

摘要： Each of divided bit line pairs is selectively connected to a sub-input/output line pair through transfer gates. A register is connected to the sub-input/output line pair. Data is transferred through the sub-input/output line pair between the register and a selected bit line pair. A sense amplifier is connected to each of the bit line pairs. Sense amplifiers are independently driven by separate sense amplifier activating signals. Therefore, even if data is transferred to the selected bit line pair from the register, fluctuations in potential on the bit line pair caused in such a case does not affect a sense amplifier activating signal connected to a non-selected bit line pair. As a result, data stored in the non-selected memory cell is prevented from being destroyed.

摘要翻译： 每个分开的位线对通过传输门选择性地连接到子输入/输出线对。 寄存器连接到子输入/输出线对。 数据通过寄存器和所选位线对之间的子输入/输出线对传输。 读出放大器连接到每个位线对。 感测放大器由独立的读出放大器激活信号驱动。 因此，即使数据从寄存器传送到所选择的位线对，在这种情况下引起的位线对上的电位波动也不影响连接到未选位线对的读出放大器激活信号。 结果，防止存储在未选择的存储单元中的数据被破坏。

公开(公告)号：US5267214A

公开(公告)日：1993-11-30

申请号：US616264

申请日：1990-11-20

申请人： Kazuyasu Fujishima ,  Yoshio Matsuda ,  Kazutami Arimoto ,  Tsukasa Ooishi ,  Masaki Tsukude

发明人： Kazuyasu Fujishima ,  Yoshio Matsuda ,  Kazutami Arimoto ,  Tsukasa Ooishi ,  Masaki Tsukude

IPC分类号： G11C11/409 ,  G11C11/401 ,  G11C11/4076 ,  G11C11/4091 ,  H01L21/8242 ,  H01L27/108 ,  G11C11/34

CPC分类号： G11C11/4091 ,  G11C11/4076

摘要： A dynamic random access memory amplifier arrangement includes a sense amplifier band shared between two different memory blocks. In this memory, only sense amplifiers related to a selected memory block are activated. The memory comprises a circuit for boosting a control signal voltage to a switching unit for connecting the selected memory block to the sense amplifiers up to a level higher than a power supply voltage Vcc during the activation of the sense amplifiers, and a circuit for separating a memory block paired with the selected memory block from the activated sense amplifiers during the sensing operation. The memory further comprises a circuit for generating a control signal of the power supply voltage Vcc and connecting all the memory blocks to the corresponding sense amplifiers in a stand-by state wherein a row address strobe signal is inactive. With this arrangement, a highly reliable memory consuming less power can be achieved which ensures data writing and/or rewriting at a full Vcc level.

摘要翻译： 动态随机存取存储器放大器装置包括在两个不同存储块之间共享的读出放大器带。 在该存储器中，只有与所选存储器块相关的读出放大器被激活。 存储器包括用于将控制信号电压升压到开关单元的电路，用于在感测放大器的激活期间将选择的存储块连接到读出放大器，直到高于电源电压Vcc的电平，以及用于分离 存储块在感测操作期间与所激活的读出放大器与选择的存储块配对。 存储器还包括用于产生电源电压Vcc的控制信号的电路，并且在行地址选通信号无效的待机状态下将所有存储块连接到相应的读出放大器。 通过这种布置，可以实现消耗更少功率的高度可靠的存储器，其确保在完全Vcc级别的数据写入和/或重写。