Abstract:
A method for forming a device isolation device of a semiconductor device is disclosed. The method includes the steps of forming a moat pattern for forming a trench on a semiconductor substrate, forming a trench by etching the semiconductor substrate to a predetermined thickness by using the moat pattern, forming a trench isolation layer by depositing a trench filling material on an entire surface of the substrate including the trench by using a high density plasma (HDP) process, partially masking a center region of the substrate and etching the trench isolation layer on edge regions of the substrate to a predetermined thickness, and planarizing the entire surface of the substrate having the trench isolation layer etched. By enhancing the thickness uniformity of the center region and the edge regions of the substrate (or wafer), when forming the trench isolation layer, by using the high density plasma (HDP) process, planarization of the trench isolation layer can be ensured even after the surface planarization process, which can minimize a difference in critical dimension depending upon the position of the center region and edge regions of the gate pattern, which is to be formed in a later process, thereby minimizing differences in device characteristics.
Abstract:
A power amplifier including a MOSFET including a source supplied with a first DC power, a gate connected to an RF input signal, and a drain connected to a power supply terminal of an RF power amplification unit; a supply voltage modulation control unit that determines a DC gate voltage of the MOSFET based on an envelope of the RF input signal; and a bypass circuit connected between the drain and the power supply terminal. The MOSFET outputs a second DC power via the drain and amplifies the RF input signal based on a third DC power substantially identical to a differential between the first and the second DC power, and also outputs an RF power via the drain. The bypass circuit receives and rectifies the RF power to supply a recycled DC power to the power supply terminal of the RF power amplification unit.
Abstract:
A power amplifier including a MOSFET including a source supplied with a first DC power, a gate connected to an RF input signal, and a drain connected to a power supply terminal of an RF power amplification unit; a supply voltage modulation control unit that determines a DC gate voltage of the MOSFET based on an envelope of the RF input signal; and a bypass circuit connected between the drain and the power supply terminal. The MOSFET outputs a second DC power via the drain and amplifies the RF input signal based on a third DC power substantially identical to a differential between the first and the second DC power, and also outputs an RF power via the drain. The bypass circuit receives and rectifies the RF power to supply a recycled DC power to the power supply terminal of the RF power amplification unit.
Abstract:
In accordance with a representative embodiment, an impedance matching circuit for use at an output stage of a power amplifier is disclosed. The impedance matching circuit comprises: an input port for receiving a frequency band signal; and a plurality of paths, each path being allocated with a principal band signal to be transmitted therethrough and including a path on-off network and a fixed-value impedance matching network. Depending on a type of the received frequency band signal, the path on-off network is configured to activate a selected one of the plurality of paths by rendering an input impedance of the selected path to have a lower absolute magnitude so that the signal is transmitted therethrough, and to deactivate the remaining paths of the plurality of paths by rendering the input impedance thereof to have a higher absolute magnitude so that the signal is not transmitted therethrough. The fixed-value impedance matching network matches a load impedance of the output port of each path to the input impedance thereof, thereby rendering the input impedance thereof to have a prescribed reference value with respect to the principal band signal when said path is activated by the path on-off network.
Abstract:
Provided are a semiconductor device and a method for manufacturing the same. The method can include: forming a gate electrode and a source/drain region on a semiconductor substrate; forming a pre metal dielectric insulation layer on the semiconductor substrate, the pre metal dielectric insulation layer including a first insulation layer using a first deposition device and a second insulation layer using a second deposition device, the second deposition device having a relatively higher deposition rate than the first deposition device; and forming a metal pattern on the pre metal dielectric layer, wherein the metal pattern electrically connects to the gate electrode and the source/drain region through the pre metal dielectric insulation layer.
Abstract:
A disk recording apparatus includes a disk to store data, a motor to rotate the disk, an encoder to generate a pulse according to the rotation of the disk, a reference signal output part to output a reference clock signal created using the pulse of the encoder, and a servo writer to record servo data on the disk in synchronization with the reference clock signal supplied from the reference signal output part. The disk recording apparatus can supply an index signal and the reference clock signal in the form of a pulse output from the encoder to detect a motor velocity.
Abstract:
An illuminating rail system comprising a rail defined by an elongate rear surface and an elongate bottom surface, the rear surface attached to a wall outside the system, the bottom surface upwardly recessed to define along the rail a front panel, a rear panel, and a furrow between the front and rear panels, with an elongate illuminator retained in the furrow.
Abstract:
The present invention relates to an optical coupling module for optically coupling an optical fiber with an optical waveguide, and a method of fabricating the optical coupling module. In an optical coupling module for optically coupling an optical network with a planar lightwave circuit (PLC), an etched groove for disposition of the optical fiber and an etched groove for mounting of the optical waveguide are exposed using a mask having mask patterns that are aligned with each other, and then anisotropically etched. By doing so, the two grooves can be precisely aligned with each other at one time, compared with a conventional method in which an exposure process is carried out two or more times. Accordingly, an inexpensive structure having high optical coupling efficiency upon manual alignment can be obtained. In addition, since a tapered structure in which an inlet is larger than a body is employed in the optical waveguide, tolerance in vertical and horizontal alignment upon manual alignment can be broaden, resulting in improvement of optical coupling efficiency and facilitation of manual alignment. Furthermore, by utilizing a thick insulation film on the substrate or a thick insulation film of the optical waveguide itself as a board, a structure for allowing assembly into and application to a high-frequency electric-optical circuit can be obtained.
Abstract:
A lower limit of a heating factor for heating control of an oxygen sensor is adjusted on the basis of the heating factor, a P-jump delay time calculated based on an output voltage of the oxygen sensor, and a diagnosis index of the oxygen sensor, and thereby an engine may be stably controlled even if the oxygen sensor is aged.
Abstract:
The invention includes a four step process for automatically finding facial images of a human face in an electronically digitized image (for example, taken by a video-camera), and classifying the age of the person (associated with the face) into an age category. For example three age categories: a baby(up to approximately age 3), a junior person(above age 3 to approximately age forty), and a senior adult (over forty years old). Categories can be further subdivided whereas every three years could be a further age category. Step 1 of the process is to find facial features of the digital image encompassing the chin, sides of the face, virtual top of the head, eyes, mouth and nose of the image. Step 2 is to compute the facial feature ratios of the facial features ratios of the facial features found in Step 1. Step 3 is to compute a wrinkle analysis of the image. Step 4 is to combine the previous two steps to categorize age of the facial image. The invention can locate and detect facial images for age classification from digital camera images and computerized generated images. The invention can be practiced in areas such as population statistic gathering for patrons at entertainment/amusement parks, television viewer ratings. Furthermore, the invention has utility in automated security/surveillance systems, demographic studies, safety monitoring systems, computer human-interface operations and automated photography. The latter to allow for point and shoot focus on specific individuals as a function of their age classification.