公开(公告)号：US07221021B2

公开(公告)日：2007-05-22

申请号：US10877450

申请日：2004-06-25

申请人： Kuo-Ming Wu ,  Chen-Bau Wu ,  Ruey-Hsin Liu ,  Shun-Liang Hsu

发明人： Kuo-Ming Wu ,  Chen-Bau Wu ,  Ruey-Hsin Liu ,  Shun-Liang Hsu

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/00

CPC分类号： H01L29/0847 ,  H01L29/7835

摘要： A high voltage device with retrograde well is disclosed. The device comprises a substrate, a gate region formed on the substrate, and a retrograde well placed in the substrate next to the gate region, wherein the retrograde well reduces a dopant concentration on the surface of the substrate, thereby minimizing damages to the gate region.

摘要翻译： 公开了具有逆行井的高压装置。 该器件包括衬底，形成在衬底上的栅极区域和位于栅极区域旁边的衬底中的逆行阱，其中逆行阱降低衬底表面上的掺杂剂浓度，从而最小化对栅极区域的损害 。

公开(公告)号：US07915677B2

公开(公告)日：2011-03-29

申请号：US12329285

申请日：2008-12-05

申请人： Tsung-Yi Huang ,  Puo-Yu Chiang ,  Ruey-Hsin Liu ,  Shun-Liang Hsu

发明人： Tsung-Yi Huang ,  Puo-Yu Chiang ,  Ruey-Hsin Liu ,  Shun-Liang Hsu

IPC分类号： H01L29/78

摘要： A semiconductor device with high breakdown voltage and low on-resistance is provided. An embodiment comprises a substrate having a buried layer in a portion of the top region of the substrate in order to extend the drift region. A layer is formed over the buried layer and the substrate, and high-voltage N-well and P-well regions are formed adjacent to each other. Field dielectrics are located over portions of the high-voltage N-wells and P-wells, and a gate dielectric and a gate conductor are formed over the channel region between the high-voltage P-well and the high-voltage N-well. Source and drain regions for the transistor are located in the high-voltage P-well and high-voltage N-well. Optionally, a P field ring is formed in the N-well region under the field dielectric. In another embodiment, a lateral power superjunction MOSFET with partition regions located in the high-voltage N-well is manufactured with an extended drift region.

公开(公告)号：US20090085101A1

公开(公告)日：2009-04-02

申请号：US12329285

申请日：2008-12-05

申请人： Tsung-Yi Huang ,  Puo-Yu Chiang ,  Ruey-Hsin Liu ,  Shun-Liang Hsu

发明人： Tsung-Yi Huang ,  Puo-Yu Chiang ,  Ruey-Hsin Liu ,  Shun-Liang Hsu

IPC分类号： H01L29/78

CPC分类号： H01L29/0847 ,  H01L29/063 ,  H01L29/0634 ,  H01L29/0878 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/7835

摘要： A semiconductor device with high breakdown voltage and low on-resistance is provided. An embodiment comprises a substrate having a buried layer in a portion of the top region of the substrate in order to extend the drift region. A layer is formed over the buried layer and the substrate, and high-voltage N-well and P-well regions are formed adjacent to each other. Field dielectrics are located over portions of the high-voltage N-wells and P-wells, and a gate dielectric and a gate conductor are formed over the channel region between the high-voltage P-well and the high-voltage N-well. Source and drain regions for the transistor are located in the high-voltage P-well and high-voltage N-well. Optionally, a P field ring is formed in the N-well region under the field dielectric. In another embodiment, a lateral power superjunction MOSFET with partition regions located in the high-voltage N-well is manufactured with an extended drift region.

摘要翻译： 提供具有高击穿电压和低导通电阻的半导体器件。 一个实施例包括在衬底的顶部区域的一部分中具有掩埋层的衬底，以便延伸漂移区域。 在掩埋层和衬底之上形成层，并且彼此相邻地形成高压N阱和P阱区。 场电介质位于高压N阱和P阱的部分上方，并且在高压P阱和高压N阱之间的沟道区上形成栅极电介质和栅极导体。 晶体管的源极和漏极区位于高压P阱和高压N阱中。 可选地，在场电介质下的N阱区域中形成P场环。 在另一个实施例中，具有位于高压N阱中的分配区域的横向功率超结MOSFET被制造为具有延伸漂移区域。

公开(公告)号：US07476591B2

公开(公告)日：2009-01-13

申请号：US11581178

申请日：2006-10-13

申请人： Tsung-Yi Huang ,  Puo-Yu Chiang ,  Ruey-Hsin Liu ,  Shun-Liang Hsu

发明人： Tsung-Yi Huang ,  Puo-Yu Chiang ,  Ruey-Hsin Liu ,  Shun-Liang Hsu

IPC分类号： H01L21/336

CPC分类号： H01L29/0847 ,  H01L29/063 ,  H01L29/0634 ,  H01L29/0878 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/7835

摘要： A semiconductor device with high breakdown voltage and low on-resistance is provided. An embodiment comprises a substrate having a buried layer in a portion of the top region of the substrate in order to extend the drift region. A layer is formed over the buried layer and the substrate, and high-voltage N-well and P-well regions are formed adjacent to each other. Field dielectrics are located over portions of the high-voltage N-wells and P-wells, and a gate dielectric and a gate conductor are formed over the channel region between the high-voltage P-well and the high-voltage N-well. Source and drain regions for the transistor are located in the high-voltage P-well and high-voltage N-well. Optionally, a P field ring is formed in the N-well region under the field dielectric. In another embodiment, a lateral power superjunction MOSFET with partition regions located in the high-voltage N-well is manufactured with an extended drift region.

摘要翻译： 提供具有高击穿电压和低导通电阻的半导体器件。 一个实施例包括在衬底的顶部区域的一部分中具有掩埋层的衬底，以便延伸漂移区域。 在掩埋层和衬底之上形成层，并且彼此相邻地形成高压N阱和P阱区。 场电介质位于高压N阱和P阱的部分上方，并且在高压P阱和高压N阱之间的沟道区上形成栅极电介质和栅极导体。 晶体管的源极和漏极区位于高压P阱和高压N阱中。 可选地，在场电介质下的N阱区域中形成P场环。 在另一个实施例中，具有位于高压N阱中的分配区域的横向功率超结MOSFET被制造为具有延伸漂移区域。

公开(公告)号：US20090001462A1

公开(公告)日：2009-01-01

申请号：US12205961

申请日：2008-09-08

申请人： Tsung-Yi Huang ,  Puo-Yu Chiang ,  Ruey-Hsin Liu ,  Shun-Liang Hsu ,  Chyi-Chyuan Huang ,  Fu-Hsin Chen ,  Eric Huang

发明人： Tsung-Yi Huang ,  Puo-Yu Chiang ,  Ruey-Hsin Liu ,  Shun-Liang Hsu ,  Chyi-Chyuan Huang ,  Fu-Hsin Chen ,  Eric Huang

IPC分类号： H01L29/76

CPC分类号： H01L29/0847 ,  H01L29/063 ,  H01L29/0634 ,  H01L29/0692 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/7835

摘要： A semiconductor structure includes a semiconductor substrate of a first conductivity type; a pre-high-voltage well (pre-HVW) in the semiconductor substrate, wherein the pre-HVW is of a second conductivity type opposite the first conductivity type; a high-voltage well (HVW) over the pre-HVW, wherein the HVW is of the second conductivity type; a field ring in the HVW and occupying a top portion of the HVW, wherein the field ring is of the first conductivity type; an insulation region over and in contact with the field ring and a portion of the HVW; a gate electrode partially over the insulation region; a drain region in the HVW, wherein the drain region is of the second conductivity type; and wherein the HVW horizontally extends further toward the drain region than the pre-HVW; and a source region adjacent to, and on an opposite side of the gate electrode than the drain region.

摘要翻译： 半导体结构包括第一导电类型的半导体衬底; 在所述半导体衬底中的预高压阱（预HVW），其中所述预HVW具有与所​​述第一导电类型相反的第二导电类型; 在HVW之前的高压井（HVW），其中HVW是第二导电类型; HVW中的场环，占据HVW的顶部，其中场环是第一导电类型; 与场环和HVW的一部分接触的绝缘区域; 位于所述绝缘区域上的栅电极; 所述HVW中的漏极区域，其中所述漏极区域是所述第二导电类型; 并且其中所述HVW水平地延伸到所述漏极区域比所述预HVW; 以及与漏极区域相邻并且在与栅极电极相反的一侧的源极区域。

公开(公告)号：US08389341B2

公开(公告)日：2013-03-05

申请号：US13175246

申请日：2011-07-01

申请人： Tsung-Yi Huang ,  Puo-Yu Chiang ,  Ruey-Hsin Liu ,  Shun-Liang Hsu ,  Chyi-Chyuan Huang ,  Fu-Hsin Chen ,  Eric Huang

发明人： Tsung-Yi Huang ,  Puo-Yu Chiang ,  Ruey-Hsin Liu ,  Shun-Liang Hsu ,  Chyi-Chyuan Huang ,  Fu-Hsin Chen ,  Eric Huang

IPC分类号： H01L21/336

CPC分类号： H01L29/0847 ,  H01L29/063 ,  H01L29/0634 ,  H01L29/0692 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/7835

摘要： A semiconductor structure includes a semiconductor substrate of a first conductivity type; a pre-high-voltage well (pre-HVW) in the semiconductor substrate, wherein the pre-HVW is of a second conductivity type opposite the first conductivity type; a high-voltage well (HVW) over the pre-HVW, wherein the HVW is of the second conductivity type; a field ring in the HVW and occupying a top portion of the HVW, wherein the field ring is of the first conductivity type; an insulation region over and in contact with the field ring and a portion of the HVW; a gate electrode partially over the insulation region; a drain region in the HVW, wherein the drain region is of the second conductivity type; and wherein the HVW horizontally extends further toward the drain region than the pre-HVW; and a source region adjacent to, and on an opposite side of the gate electrode than the drain region.

摘要翻译： 半导体结构包括第一导电类型的半导体衬底; 在所述半导体衬底中的预高压阱（预HVW），其中所述预HVW具有与所​​述第一导电类型相反的第二导电类型; 在HVW之前的高压井（HVW），其中HVW是第二导电类型; HVW中的场环，占据HVW的顶部，其中场环是第一导电类型; 与场环和HVW的一部分接触的绝缘区域; 位于所述绝缘区域上的栅电极; 所述HVW中的漏极区域，其中所述漏极区域是所述第二导电类型; 并且其中所述HVW水平地延伸到所述漏极区域比所述预HVW; 以及与漏极区域相邻并且在与栅极电极相反的一侧的源极区域。

公开(公告)号：US20120003803A1

公开(公告)日：2012-01-05

申请号：US13175246

申请日：2011-07-01

申请人： Tsung-Yi Huang ,  Puo-Yu Chiang ,  Ruey-Hsin Liu ,  Shun-Liang Hsu ,  Chyi-Chyuan Huang ,  Fu-Hsin Chen ,  Eric Huang

发明人： Tsung-Yi Huang ,  Puo-Yu Chiang ,  Ruey-Hsin Liu ,  Shun-Liang Hsu ,  Chyi-Chyuan Huang ,  Fu-Hsin Chen ,  Eric Huang

IPC分类号： H01L21/336

CPC分类号： H01L29/0847 ,  H01L29/063 ,  H01L29/0634 ,  H01L29/0692 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/7835

摘要： A semiconductor structure includes a semiconductor substrate of a first conductivity type; a pre-high-voltage well (pre-HVW) in the semiconductor substrate, wherein the pre-HVW is of a second conductivity type opposite the first conductivity type; a high-voltage well (HVW) over the pre-HVW, wherein the HVW is of the second conductivity type; a field ring in the HVW and occupying a top portion of the HVW, wherein the field ring is of the first conductivity type; an insulation region over and in contact with the field ring and a portion of the HVW; a gate electrode partially over the insulation region; a drain region in the HVW, wherein the drain region is of the second conductivity type; and wherein the HVW horizontally extends further toward the drain region than the pre-HVW; and a source region adjacent to, and on an opposite side of the gate electrode than the drain region.

摘要翻译： 半导体结构包括第一导电类型的半导体衬底; 在所述半导体衬底中的预高压阱（预HVW），其中所述预HVW具有与所​​述第一导电类型相反的第二导电类型; 在HVW之前的高压井（HVW），其中HVW是第二导电类型; HVW中的场环，占据HVW的顶部，其中场环是第一导电类型; 与场环和HVW的一部分接触的绝缘区域; 位于所述绝缘区域上的栅电极; 所述HVW中的漏极区域，其中所述漏极区域是所述第二导电类型; 并且其中所述HVW水平地延伸到所述漏极区域比所述预HVW; 以及与漏极区域相邻并且在与栅极电极相反的一侧的源极区域。

公开(公告)号：US20100203691A1

公开(公告)日：2010-08-12

申请号：US12760182

申请日：2010-04-14

申请人： Chen-Bau Wu ,  Chien-Shao Tang ,  Robin Hsieh ,  Ruey-Hsin Liu ,  Shun-Liang Hsu

发明人： Chen-Bau Wu ,  Chien-Shao Tang ,  Robin Hsieh ,  Ruey-Hsin Liu ,  Shun-Liang Hsu

IPC分类号： H01L21/8234 ,  H01L21/336

CPC分类号： H01L27/092 ,  H01L21/823814 ,  H01L21/823892 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/0852 ,  H01L29/1083 ,  H01L29/7816 ,  H01L29/7835

摘要： A transistor suitable for high-voltage applications is provided. The transistor is formed on a substrate having a deep well of a first conductivity type. A first well of the first conductivity type and a second well of a second conductivity type are formed such that they are not immediately adjacent each other. The well of the first conductivity type and the second conductivity type may be formed simultaneously as respective wells for low-voltage devices. In this manner, the high-voltage devices may be formed on the same wafer as low-voltage devices with fewer process steps, thereby reducing costs and process time. A doped isolation well may be formed adjacent the first well on an opposing side from the second well to provide further device isolation.

摘要翻译： 提供了适用于高压应用的晶体管。 晶体管形成在具有第一导电类型的深阱的衬底上。 形成第一导电类型的第一阱和第二导电类型的第二阱，使得它们不彼此紧邻。 第一导电类型和第二导电类型的阱可以同时形成用于低电压装置的各个孔。 以这种方式，高压器件可以与具有较少工艺步骤的低电压器件形成在相同的晶片上，从而降低成本和处理时间。 可以在与第二阱相对的一侧上邻近第一阱形成掺杂隔离阱以提供进一步的器件隔离。

公开(公告)号：US07719064B2

公开(公告)日：2010-05-18

申请号：US12100888

申请日：2008-04-10

申请人： Chen-Bau Wu ,  Chien-Shao Tang ,  Robin Hsieh ,  Ruey-Hsin Liu ,  Shun-Liang Hsu

发明人： Chen-Bau Wu ,  Chien-Shao Tang ,  Robin Hsieh ,  Ruey-Hsin Liu ,  Shun-Liang Hsu

IPC分类号： H01L29/78

CPC分类号： H01L27/092 ,  H01L21/823814 ,  H01L21/823892 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/0852 ,  H01L29/1083 ,  H01L29/7816 ,  H01L29/7835

摘要： A transistor suitable for high-voltage applications is provided. The transistor is formed on a substrate having a deep well of a first conductivity type. A first well of the first conductivity type and a second well of a second conductivity type are formed such that they are not immediately adjacent each other. The well of the first conductivity type and the second conductivity type may be formed simultaneously as respective wells for low-voltage devices. In this manner, the high-voltage devices may be formed on the same wafer as low-voltage devices with fewer process steps, thereby reducing costs and process time. A doped isolation well may be formed adjacent the first well on an opposing side from the second well to provide further device isolation.

摘要翻译： 提供了适用于高压应用的晶体管。 晶体管形成在具有第一导电类型的深阱的衬底上。 形成第一导电类型的第一阱和第二导电类型的第二阱，使得它们不彼此紧邻。 第一导电类型和第二导电类型的阱可以同时形成用于低电压装置的各个孔。 以这种方式，高压器件可以与具有较少工艺步骤的低电压器件形成在相同的晶片上，从而降低成本和处理时间。 可以在与第二阱相对的一侧上邻近第一阱形成掺杂隔离阱以提供进一步的器件隔离。

公开(公告)号：US20070132033A1

公开(公告)日：2007-06-14

申请号：US11301203

申请日：2005-12-12

申请人： Chen-Bau Wu ,  Chien-Shao Tang ,  Robin Hsieh ,  Ruey-Hsin Liu ,  Shun-Liang Hsu

发明人： Chen-Bau Wu ,  Chien-Shao Tang ,  Robin Hsieh ,  Ruey-Hsin Liu ,  Shun-Liang Hsu

IPC分类号： H01L29/76

CPC分类号： H01L27/092 ,  H01L21/823814 ,  H01L21/823892 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/0852 ,  H01L29/1083 ,  H01L29/7816 ,  H01L29/7835

摘要： A transistor suitable for high-voltage applications is provided. The transistor is formed on a substrate having a deep well of a first conductivity type. A first well of the first conductivity type and a second well of a second conductivity type are formed such that they are not immediately adjacent each other. The well of the first conductivity type and the second conductivity type may be formed simultaneously as respective wells for low-voltage devices. In this manner, the high-voltage devices may be formed on the same wafer as low-voltage devices with fewer process steps, thereby reducing costs and process time. A doped isolation well may be formed adjacent the first well on an opposing side from the second well to provide further device isolation.

摘要翻译： 提供了适用于高压应用的晶体管。 晶体管形成在具有第一导电类型的深阱的衬底上。 形成第一导电类型的第一阱和第二导电类型的第二阱，使得它们不彼此紧邻。 第一导电类型和第二导电类型的阱可以同时形成用于低电压装置的各个孔。 以这种方式，高压器件可以与具有较少工艺步骤的低电压器件形成在相同的晶片上，从而降低成本和处理时间。 可以在与第二阱相对的一侧上邻近第一阱形成掺杂隔离阱以提供进一步的器件隔离。