-
公开(公告)号：US08329584B2
公开(公告)日：2012-12-11
申请号：US13151867
申请日：2011-06-02
申请人： Toshiyuki Takewaki , Manabu Iguchi , Daisuke Oshida , Hironori Toyoshima , Masayuki Hiroi , Takuji Onuma , Hiroaki Nanba , Ichiro Honma , Mieko Hasegawa , Yasuaki Tsuchiya , Toshiji Taiji , Takaharu Kunugi
发明人： Toshiyuki Takewaki , Manabu Iguchi , Daisuke Oshida , Hironori Toyoshima , Masayuki Hiroi , Takuji Onuma , Hiroaki Nanba , Ichiro Honma , Mieko Hasegawa , Yasuaki Tsuchiya , Toshiji Taiji , Takaharu Kunugi
IPC分类号： H01L21/44
CPC分类号： H01L21/02074 , H01L21/76883
摘要： A post-CMP cleaning process of a copper layer is to be performed as follows. An alkaline aqueous solution, a polycarboxylic acid, BTA, and an alkaline aqueous solution are sequentially brought into contact with a primary surface of a silicon substrate over which the copper layer is provided.
摘要翻译： 如下进行铜层的CMP后清洗工序。 依次使碱性水溶液，多元羧酸，BTA和碱性水溶液与设置有铜层的硅基板的主面接触。
-
公开(公告)号：US20060216946A1
公开(公告)日：2006-09-28
申请号：US11156735
申请日：2005-06-21
IPC分类号： H01L21/473
CPC分类号： H01L21/31144 , H01L21/02164 , H01L21/02271 , H01L21/02274 , H01L21/31612
摘要： An intermediate film 222 in a three-layered resist film 225 is formed by the chemical vapor deposition process at a temperature not higher than 300° C., using Si(OR1)(OR2)(OR3)(OR4) , where each of R1, R2, R3 and R4 independently represents a carbon-containing group or a hydrogen atom, excluding the case where all of R1 to R4 are hydrogen atoms.
摘要翻译： 在三层抗蚀剂膜225中的中间膜222通过化学气相沉积工艺在不高于300℃的温度下，使用Si（OR 2）（OR 2） （OR 3）（OR 4），其中R 1，R 2，R 2， R 3和R 4独立地代表含碳基团或氢原子，不包括所有R 1至R“ SUB> 4 是氢原子。
-
公开(公告)号：US5432037A
公开(公告)日：1995-07-11
申请号：US977563
申请日：1992-11-17
CPC分类号： G03G13/025 , G03G13/09 , G03G9/097 , Y10S430/102
摘要： Disclosed herein are an image-forming process which comprises steps of:uniformly charging a latent image carrier by a charging member disposed in contact with or in close vicinity to the latent image carrier,forming a latent image pattern on the latent image carrier by exposure,developing the formed latent image pattern with a developer composed of image-developing particles and conductive particles having an average particle size of smaller than that of said image-developing particles, thereby transferring at least said image-developing particles in the developer to the latent image carrier, andtransferring the image-developing particles transferred to the latent image carrier, to a transfer material; a developer for use in the image-forming process; and an image-forming system.
摘要翻译： 本文公开了一种图像形成方法，其包括以下步骤：通过与潜像载体接触或紧邻设置的充电部件对潜像载体进行均匀充电，通过曝光在潜像载体上形成潜像图案， 用由图像显影颗粒和平均粒径小于所述显影颗粒的导电颗粒的显影剂显影形成的潜像图案，从而将显影剂中的至少所述图像显影颗粒转印到潜像 载体，并将转印到潜像载体上的图像显影粒子转印到转印材料上; 用于图像形成过程的显影剂; 和图像形成系统。
-
公开(公告)号：US07294932B2
公开(公告)日：2007-11-13
申请号：US11183820
申请日：2005-07-19
申请人： Masayuki Hiroi
发明人： Masayuki Hiroi
IPC分类号： H01L23/48
CPC分类号： H01L23/522 , H01L21/7684 , H01L21/78 , H01L23/5226 , H01L23/585
摘要： The semiconductor device 100 includes a multilayer wiring structure formed on the semiconductor substrate. The multilayer wiring structure includes at least a first inter layer dielectric film 120 in which interconnects 124 are formed, and at least a second inter layer dielectric film 122 in which vias 126 are formed. The multilayer wiring structure includes a circuit region 110 in which the interconnects 124 and the vias 126 are formed, a seal ring region 112 formed around the circuit region 110 and in which seal rings surrounding the circuit region 110 in order to seal the circuit region 110 are formed, and a peripheral region 114 formed around the seal ring region 112. The semiconductor device 100 further includes dummy vias 136 formed of a metal material, formed in the second interlayer dielectric film 122 at the peripheral region 114.
摘要翻译： 半导体器件100包括形成在半导体衬底上的多层布线结构。 多层布线结构至少包括形成有互连件124的第一层间电介质膜120和至少形成有通孔126的第二层间电介质膜122。 多层布线结构包括其中形成有互连件124和通孔126的电路区域110，围绕电路区域110形成的密封环区域112，围绕电路区域110的密封环以密封电路区域110 以及围绕密封环区域112形成的周边区域114。 半导体器件100还包括在周边区域114处形成在第二层间电介质膜122中的由金属材料形成的虚拟通孔136。
-
15.发明申请Method of semiconductor device and design supporting system of semiconductor device 有权半导体器件的方法和半导体器件的设计支持系统公开(公告)号：US20070033563A1
公开(公告)日：2007-02-08
申请号：US11498813
申请日：2006-08-04
申请人： Masayuki Hiroi
发明人： Masayuki Hiroi
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： A designing method of a semiconductor device is achieved by setting interconnection reference data indicating permissible interconnection widths which are discrete, and a permissible interval between adjacent two of interconnections, the interconnection intervals being discrete; and by specifying an interconnection relating an impermissible width and interconnections relating to an impermissible interval from the interconnections for a semiconductor device based on the interconnection data. The permissible widths and the permissible intervals are preferably equal to or larger than a minimum design dimension.
摘要翻译： 半导体器件的设计方法是通过设置表示离散的允许互连宽度的互连参考数据和相邻两个互连之间的允许间隔，互连间隔是离散的来实现的; 并且通过基于互连数据指定与不允许宽度相关的互连和与不允许间隔相关的互连与半导体器件的互连。 优选允许宽度和容许间隔等于或大于最小设计尺寸。
-
公开(公告)号：US20060113685A1
公开(公告)日：2006-06-01
申请号：US10538306
申请日：2003-09-22
IPC分类号： H01L23/48
CPC分类号： H01L23/53233 , H01L21/76883 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： A wiring metal contains a polycrystal of copper (Cu) as a primary element and an additional element other than Cu, and concentration of the additional element is, at crystal grain boundaries composing the Cu polycrystal and in vicinities of the crystal grain boundaries, higher than that of the inside of the crystal grains. The additional element is preferably at least one element selected from a group consisting of Ti, Zr, Hf, Cr, Co, Al, Sn, Ni, Mg, and Ag. This Cu wiring is formed by forming a Cu polycrystalline film, forming an additional element layer on this Cu film, and diffusing this additional element from the additional element layer into the Cu film. This copper alloy for wiring is preferred as metal wiring formed for a semiconductor device.
-
公开(公告)号：US07955980B2
公开(公告)日：2011-06-07
申请号：US12543128
申请日：2009-08-18
申请人： Toshiyuki Takewaki , Manabu Iguchi , Daisuke Oshida , Hironori Toyoshima , Masayuki Hiroi , Takuji Onuma , Hiroaki Nanba , Ichiro Honma , Mieko Hasegawa , Yasuaki Tsuchiya , Toshiji Taiji , Takaharu Kunugi
发明人： Toshiyuki Takewaki , Manabu Iguchi , Daisuke Oshida , Hironori Toyoshima , Masayuki Hiroi , Takuji Onuma , Hiroaki Nanba , Ichiro Honma , Mieko Hasegawa , Yasuaki Tsuchiya , Toshiji Taiji , Takaharu Kunugi
IPC分类号： H01L21/44
CPC分类号： H01L21/02074 , H01L21/76883
摘要： A post-CMP cleaning process of a copper layer is to be performed as follows. An alkaline aqueous solution, a polycarboxylic acid, BTA, and an alkaline aqueous solution are sequentially brought into contact with a primary surface of a silicon substrate over which the copper layer is provided.
摘要翻译： 如下进行铜层的CMP后清洗工序。 依次使碱性水溶液，多元羧酸，BTA和碱性水溶液与设置有铜层的硅基板的主面接触。
-
公开(公告)号：US07663240B2
公开(公告)日：2010-02-16
申请号：US11329045
申请日：2006-01-11
申请人： Masayuki Hiroi
发明人： Masayuki Hiroi
IPC分类号： H01L23/52
CPC分类号： H01L23/564 , H01L23/585 , H01L2924/0002 , H01L2924/00
摘要： Mechanical strength and moisture resistance of a multilayer interconnect structure is to be improved. A semiconductor device includes a circuit region and a seal ring region formed around the circuit region, on a semiconductor substrate. The seal ring region includes a plurality of interconnect layers including interconnect lines and a plurality of via layers including a plurality of slit vias stacked on one another, and a pitch between the slit vias in at least one of the via layers (lower or middle layer) is different from a pitch between the slit vias in other via layers (upper layer).
摘要翻译： 要提高多层互连结构的机械强度和耐湿性。 半导体器件包括在半导体衬底上形成在电路区域周围的电路区域和密封环区域。 密封圈区域包括多个互连层，包括互连线和包括彼此堆叠的多个狭缝通孔的多个通孔层，以及至少一个通孔层中的狭缝通孔之间的间距（下层或中间层 ）不同于其它通孔层（上层）中的狭缝通孔之间的间距。
-
公开(公告)号：US20080160750A1
公开(公告)日：2008-07-03
申请号：US11953127
申请日：2007-12-10
申请人： Toshiyuki TAKEWAKI , Manabu Iguchi , Daisuke Oshida , Hironori Toyoshima , Masayuki Hiroi , Takuji Onuma , Hiroaki Nanba , Ichiro Honma , Mieko Hasegawa , Yasuaki Tsuchiya , Toshiji Taiji , Takahara Kunugi
发明人： Toshiyuki TAKEWAKI , Manabu Iguchi , Daisuke Oshida , Hironori Toyoshima , Masayuki Hiroi , Takuji Onuma , Hiroaki Nanba , Ichiro Honma , Mieko Hasegawa , Yasuaki Tsuchiya , Toshiji Taiji , Takahara Kunugi
IPC分类号： H01L21/302 , H01L21/44
CPC分类号： H01L21/02074 , H01L21/76883
摘要： A post-CMP cleaning process of a copper layer is to be performed as follows. An alkaline aqueous solution, a polycarboxylic acid, BTA, and an alkaline aqueous solution are sequentially brought into contact with a primary surface of a silicon substrate over which the copper layer is provided.
摘要翻译： 如下进行铜层的CMP后清洗工序。 依次使碱性水溶液，多元羧酸，BTA和碱性水溶液与设置有铜层的硅基板的主面接触。
-
公开(公告)号：US20060022224A1
公开(公告)日：2006-02-02
申请号：US11183820
申请日：2005-07-19
申请人： Masayuki Hiroi
发明人： Masayuki Hiroi
IPC分类号： H01L29/768
CPC分类号： H01L23/522 , H01L21/7684 , H01L21/78 , H01L23/5226 , H01L23/585
摘要： The semiconductor device 100 includes a multilayer wiring structure formed on the semiconductor substrate. The multilayer wiring structure includes at least a first inter layer dielectric film 120 in which interconnects 124 are formed, and at least a second inter layer dielectric film 122 in which vias 126 are formed. The multilayer wiring structure includes a circuit region 110 in which the interconnects 124 and the vias 126 are formed, a seal ring region 112 formed around the circuit region 110 and in which seal rings surrounding the circuit region 110 in order to seal the circuit region 110 are formed, and a peripheral region 114 formed around the seal ring region 112. The semiconductor device 100 further includes dummy vias 136 formed of a metal material, formed in the second interlayer dielectric film 122 at the peripheral region 114.
摘要翻译： 半导体器件100包括形成在半导体衬底上的多层布线结构。 多层布线结构至少包括形成有互连件124的第一层间电介质膜120和至少形成有通孔126的第二层间电介质膜122。 多层布线结构包括其中形成有互连件124和通孔126的电路区域110，围绕电路区域110形成的密封环区域112，围绕电路区域110的密封环以密封电路区域110 以及围绕密封环区域112形成的周边区域114。 半导体器件100还包括在周边区域114处形成在第二层间电介质膜122中的由金属材料形成的虚拟通孔136。
-
-
-
-
-
-
-
-
-
搜索结果
29 条记录 (耗时 0.037 秒)
