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公开(公告)号：US20100008441A1
公开(公告)日：2010-01-14
申请号：US12375655
申请日：2007-07-31
CPC分类号： H04L1/005 , H03M13/11 , H03M13/27 , H03M13/2957 , H04B7/04 , H04L1/1829 , H04L25/03318 , H04L25/067 , H04L2025/03426
摘要： A multiantenna receiving device is provided to make it possible to cope with both improvement in error rate characteristic and simplification in structure. The multiantenna receiving device is comprised of soft judgement output units (520_A, 522_A, 524_B, 526_B) for carrying out a soft judgement of a modulation signal in accordance with signal point distances between a plurality of candidate signal points with respect to a plurality of multiplexed modulation signals and a receiving signal, decoding units (528_A, 528_B) for obtaining digital data of the modulation signals by using the judged results obtained by the soft judgement output units (520_A, 522_A, 524_B, 526_B), and signal point decreasing units (512_YA, 512_XA, 514_YA, 514_XA, 516_YB, 516_XB, 518_YB, 518_XB) for decreasing the number of the candidate signal points used in the soft judgement output units (520_A, 522_A, 524_B, 526_B) by recursively using a part of the digital data except self-modulation signals obtained by the decoding units (528_A, 528_B).
摘要翻译： 提供了一种多天线接收装置，以便能够应对错误率特性的提高和结构简化。 多天线接收装置包括软判断输出单元（520_A，522_A，524_B，526_B），用于根据多个候选信号点之间的信号点距离执行调制信号的软判断 调制信号和接收信号，用于通过使用由软判断输出单元（520_A，522_A，524_B，526_B）获得的判断结果获得调制信号的数字数据的解码单元（528_A，528_B）和信号点减少单元 512_YA，512_XA，514_YA，514_XA，516_YB，516_XB，518_YB，518_XB），用于通过递归地使用一部分数字数据来减少软判断输出单元（520_A，522_A，524_B，526_B）中使用的候选信号点的数量 除了由解码单元（528_A，528_B）获得的自调制信号之外。
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公开(公告)号：US08473827B2
公开(公告)日：2013-06-25
申请号：US13122942
申请日：2009-10-09
申请人： Yutaka Murakami , Shutai Okamura
发明人： Yutaka Murakami , Shutai Okamura
IPC分类号： H03M13/03
CPC分类号： H03M13/116 , H03M13/005 , H03M13/1125 , H03M13/15 , H03M13/616 , H03M13/6362 , H03M13/6527 , H04L1/0041
摘要： Disclosed are an encoder, a transmission device, and an encoding method with which the transmission amount is reduced and a deterioration in transmission efficiency is suppressed while improving reception quality when QC-LDPC or a like block encoding is used. A puncture pattern setting unit (620) searches for a puncture pattern for each integral multiple of the number of columns or for each divisor of the number of columns of a sub block matrix that forms a check matrix (H) of a QC-LDPC code, and a puncture unit (data reduction unit) (630) switches the puncture pattern for each integral multiple of the number of columns or for each divisor of the number of columns of the sub block matrix that forms the check matrix of the QC-LDPC code.
摘要翻译： 公开了一种编码器，发送装置和编码方法，其中，当使用QC-LDPC等类型块编码时，在提高接收质量的同时，传输量减少并且抑制传输效率的劣化。 穿刺图案设置单元（620）针对形成QC-LDPC码的校验矩阵（H）的子块矩阵的列数的每个整数倍的每个整数倍或每个除数的数量的每个除数搜索穿孔图案 ，并且穿刺单元（数据缩小单元）（630）针对形成QC-LDPC的校验矩阵的子块矩阵的列数的每个整数倍或每个除数的每个除数的整数倍切换穿孔图案 码。
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13.发明授权Low-density parity check convolution code (LDPC-CC) encoder and LDPC-CC decoder 有权低密度奇偶校验卷积码（LDPC-CC）编码器和LDPC-CC解码器公开(公告)号：US08423876B2
公开(公告)日：2013-04-16
申请号：US12668655
申请日：2008-07-11
IPC分类号： H03M13/03
CPC分类号： H03M13/118 , H03M13/1111 , H03M13/1154 , H03M13/23 , H03M13/235 , H03M13/6362
摘要： It is possible to provide and an LDPC-CC (Low-Density Parity-Check Convolution Codes) encoder and an LDPC-CC decoder which performs an error correction encoding and decoding while reducing the amount of a termination sequence required for encoding/decoding the LDPC-CC encoding/decoding and suppressing degradation of the transmission efficiency. The LDPC-CC encoder (400) includes a weight control unit (470) which stores a weight pattern (475) based on an LDPC-CC inspection matrix (100); and a weight pattern (476) based on a check matrix (300) obtained by deforming an LDPC-CC inspection matrix (100). The weight control unit (470) controls a weight to be multiplied onto the outputs of a plurality of shift registers (410-1 to 410-M, 430-1 to 430-M) by using the weight pattern (475) when the input bit is an information sequence, and using a weight pattern (476) which makes a weight value to be multiplied by an inspection bit v2,t to be 0 when the input bit is a termination sequence.
摘要翻译： 可以提供LDPC-CC（低密度奇偶校验卷积码）编码器和LDPC-CC解码器，该LDPC-CC解码器在减少LDPC编码/解码所需的终止序列的量的同时进行纠错编码和解码 -CC编码/解码并抑制传输效率的降低。 LDPC-CC编码器（400）包括：权重控制单元（470），其基于LDPC-CC检查矩阵（100）存储权重模式（475）; 以及基于通过使LDPC-CC检查矩阵（100）变形而获得的校验矩阵（300）的权重模式（476）。 权重控制单元（470）通过使用加权模式（475）来控制要乘以多个移位寄存器（410-1至410-M，430-1至430-M）的输出的权重 位是信息序列，并且当输入比特是终止序列时，使用使加权值乘以检查比特v2的加权模式（476），t为0。
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公开(公告)号：US08401110B2
公开(公告)日：2013-03-19
申请号：US12447885
申请日：2007-11-01
CPC分类号： H04L1/0071 , H03M13/15 , H04L1/0003 , H04L1/0009 , H04L1/0059 , H04L1/22 , H04L5/0007 , H04L27/0008 , H04L27/2647 , H04L27/36 , H04L27/38
摘要： A transmitter apparatus wherein a simple structure is used to successfully suppress the degradation of error rate performance that otherwise would be caused by fading or the like. There are included encoding parts (11—1-11—4) that encode transport data; a mapping part (3304) that performs such a mapping that encoded data sequentially formed by the encoding parts (11—1-11—4) are not successively included in the same symbol, thereby forming data symbols; and a symbol interleaver (3301) that interleaves the data symbols. In this way, a low computational complexity can be used to perform an interleaving process equivalent to a bit interleaving process to effectively improve the reception quality at a receiving end.
摘要翻译： 一种发射机装置，其中使用简单的结构来成功地抑制否则将由衰落等引起的误码率性能的降级。 包括编码传输数据的编码部分（11-1-11-4）; 执行编码由编码部分（11-1-11-4）顺序形成的数据的映射的映射部分（3304）不被连续地包括在相同的符号中，从而形成数据符号; 以及交错数据符号的符号交织器（3301）。 以这种方式，可以使用低的计算复杂度来执行等同于比特交织处理的交织处理，以有效地提高接收端的接收质量。
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公开(公告)号：US08286064B2
公开(公告)日：2012-10-09
申请号：US12738621
申请日：2008-10-30
IPC分类号： G06F11/00
CPC分类号： H03M13/1102 , H03M13/23 , H03M13/255 , H03M13/356 , H03M13/373 , H03M13/6362 , H04L1/005 , H04L1/0057 , H04L1/0059 , H04L1/0069 , H04L1/0071 , H04L1/06 , H04L5/0044 , H04L27/2626 , H04L27/3422
摘要： Provided is a transmission device which improves the error rate characteristic upon decoding when performing error correction encoding by using a self-orthogonal code or an LDPC-CC in a communication system using a communication path having a fading fluctuation, multi-value modulation, or MIMO transmission. In the transmission device, the self-orthogonal encoding unit (110) encodes a self-orthogonal code having a constriction length K and an interleave unit (130) rearranges a code word sequence so that the same modulation symbol includes an information bit of a moment i and a non-correlated bit of the information bit of the moment i in a multi-value modulation unit (150).
摘要翻译： 提供一种传输装置，其在使用具有衰落波动，多值调制或MIMO的通信路径的通信系统中通过使用自正交码或LDPC-CC进行纠错编码时，提高解码时的错误率特性 传输。 在发送装置中，自正交编码单元（110）编码具有收缩长度K的自正交码和交织单元（130）重新排列码字序列，使得相同的调制符号包括一个信息位 i和多值调制单元（150）中的时刻i的信息比特的非相关比特。
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公开(公告)号：US08121227B2
公开(公告)日：2012-02-21
申请号：US12882989
申请日：2010-09-15
CPC分类号： H04L27/38 , H04B7/04 , H04L25/03184 , H04L25/067 , H04L2025/0342 , H04L2025/03426
摘要： It is possible to demodulate a plurality of modulated signals transmitted from a plurality of antennas by using a comparatively small-size circuit with a preferable error ratio characteristic. Partial bit judgment units (509, 512) demodulates partial bits of the 64QAM-modulated signal by modifying which of the bits in the 6-bit strings constituting a symbol is to be demodulated depending on in which region of the IQ plane the reception signal point exists. This improves the partial bit error characteristic judged by the partial bit judgment units (509, 512), which in turn improves reliability of the reduced candidate signal point for use by a likelihood detection unit (518). As a result, it is possible to improve the error ratio characteristic of the final reception digital signals (322, 323).
摘要翻译： 可以通过使用具有优选误差比特性的较小尺寸的电路来解调从多个天线发送的多个调制信号。 部分位判断单元（509,512）通过根据IQ平面的哪个区域修改构成符号的6位串中的哪个位要解调64QAM调制信号的部分位，接收信号点 存在 这改善了由部分比特判断单元（509,512）判断的部分比特误差特性，这又提高了可靠性检测单元（518）使用的缩减候补信号点的可靠性。 结果，可以提高最终接收数字信号（322,323）的误差比特性。
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公开(公告)号：US20100269009A1
公开(公告)日：2010-10-21
申请号：US12745216
申请日：2008-12-18
CPC分类号： H03M13/255 , H03M13/1128 , H03M13/116 , H03M13/118 , H03M13/23 , H03M13/6362 , H03M13/6502 , H03M13/6527
摘要： There is provided an encoder that provides a termination sequence with a simple structure for LDPC-CC encoding and reduces an amount of the termination sequence transmitted to a transmission line. The LDPC-CC encoder (200) connects a first encoder (230) to a second encoder (240) to perform encoding and thereby carry out LDPC-CC encoding, the first encoder (230) performing encoding based on an partial parity check matrix for information bits (110) obtained by extracting a sequence corresponding to the information bits in a parity check matrix (100) and the second encoder (240) performing encoding based on a partial parity check matrix for parity bits (120) obtained by extracting a sequence corresponding to the parity bits in the parity check matrix (100). A termination sequence generator (210) generates a termination sequence including the same number of bits as the memory length of the first encoder (230) and provides the generated termination sequence as an input sequence.
摘要翻译： 提供了一种编码器，其提供具有用于LDPC-CC编码的简单结构的终止序列，并减少发送到传输线的终止序列的量。 LDPC-CC编码器（200）将第一编码器（230）连接到第二编码器（240）以执行编码，从而执行LDPC-CC编码，第一编码器（230）基于部分奇偶校验矩阵执行编码， 通过提取与奇偶校验矩阵（100）中的信息比特相对应的序列获得的信息比特（110）和基于通过提取序列获得的奇偶校验比特（120）的部分奇偶校验矩阵执行编码的第二编码器（240） 对应于奇偶校验矩阵（100）中的奇偶校验位。 终止序列生成器（210）生成包括与第一编码器（230）的存储器长度相同数量的位的终止序列，并且将生成的终止序列提供为输入序列。
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公开(公告)号：US20100192047A1
公开(公告)日：2010-07-29
申请号：US12668829
申请日：2008-07-11
CPC分类号： H04L1/0057 , H03M13/1111 , H03M13/235 , H03M13/2707 , H03M13/353 , H03M13/6306 , H04L1/0059 , H04L1/1812 , H04L5/0007 , H04L5/0042
摘要： A transmitting device and method enabling improvement of the reception quality on the receiving side when the LDPC-CC (Low-Density Parity-Check Convolutional Codes) encoding is used. The transmitting device (100) comprises an LDPC-CC encoding section (102), a sorting section (121) for sorting the encoded data (120) acquired by the LDPC-CC encoding section (102) into a first encoded data set (103_A) corresponding to the column number of the column containing “1” in a part of an LDPC-CC check matrix H from which a protograph is excluded and a second encoded data set (103_B) corresponding to the column numbers of the columns other than that, and a frame constructing section (a control section (106)) for constructing a transmission frame where the first and second encoded data sets (103_A, 103_B) are arranged in positions different in time or frequency in the transmission frame.
摘要翻译： 当使用LDPC-CC（低密度奇偶校验卷积码）编码时，能够提高接收侧的接收质量的发送装置和方法。 发送设备（100）包括LDPC-CC编码部分（102），用于将由LDPC-CC编码部分（102）获取的编码数据（120）分类为第一编码数据集（103_A）的排序部分 ）对应于从其排除原型图的LDPC-CC校验矩阵H的一部分中包含“1”的列的列号，以及对应于除此之外的列的列号的第二编码数据集（103_B） ，以及用于构造传输帧的帧构造部（控制部（106）），其中第一和第二编码数据集（103_A，103_B）被布置在传输帧中的时间或频率不同的位置。
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公开(公告)号：US20100180176A1
公开(公告)日：2010-07-15
申请号：US12377107
申请日：2007-08-31
申请人： Naoya Yosoku , Shutai Okamura , Yutaka Murakami
发明人： Naoya Yosoku , Shutai Okamura , Yutaka Murakami
CPC分类号： H03M13/1188 , H03M13/1185
摘要： An encoding method by which an encoding speed is improved is disclosed. An encoder (100) comprises an input data storage section (107) for outputting the stored input data (D100) according to an output control signal (108), an input data count section (101) for counting the inputs of input data (D100), an output control section (102) for controlling the output destination of the input data (D100) according to the input counts, one-bit storage sections (103-1 to 103-(N−K)) for holding one-bit data, row-vector storage sections (104-1 to 104-K) for holding row vectors of an LDPC code creation matrix, vector multiplying sections (105-1 to 105-K) for multiplying a row vector and a column vector, a parity storage section (109) for holding a parity created by the multiplication, and an LDPC code-word series creating section (106); for creating an LDPC code word from the input data series and parity series and outputting it.
摘要翻译： 公开了一种提高编码速度的编码方法。 编码器（100）包括输入数据存储部（107），用于根据输出控制信号（108）输出所存储的输入数据（D100）;输入数据计数部分（101），用于对输入数据（D100 ），用于根据输入计数控制输入数据（D100）的输出目的地的输出控制部分（102），用于保持一位的一位存储部分（103-1至103-（N-K）） 用于保持LDPC码产生矩阵的行向量的数据，行向量存储部分（104-1至104-K），用于乘以行向量和列向量的向量相乘部分（105-1至105-K）， 奇偶校验存储部（109），用于保持乘法生成的奇偶校验; LDPC码字序列生成部（106）; 用于从输入数据序列和奇偶校验序列创建LDPC码字并将其输出。
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公开(公告)号：US08219865B2
公开(公告)日：2012-07-10
申请号：US13190158
申请日：2011-07-25
CPC分类号： H04L1/0041 , H03M13/13 , H03M13/255 , H03M13/2721 , H03M13/2909 , H04L1/0003 , H04L1/0057 , H04L1/0071 , H04L1/0656 , H04L5/0023
摘要： A transmitter apparatus wherein a relatively simple structure is used to suppress burst errors without changing the block sizes of encoded blocks even when the number of modulation multi-values is increased. An encoding part subjects transport data to a block encoding process to form block encoded data. A modulating part modulates the block encoded data to form data symbols; and an arranging (interleaving) part arranges (interleaves) the block encoded data in such a manner that the intra-block encoded data of the encoded blocks, which include their respective single different data symbol, get together, and then supplies the arranged (interleaved) block encoded data to the modulating part. In this way, there can be provided a transmitter apparatus wherein a relatively simple structure is used to suppress burst errors without changing the block sizes of encoded blocks even when the number of modulation multi-values is increased.
摘要翻译： 一种发射机装置，即使当调制多值的数量增加时，使用相对简单的结构来抑制突发错误，而不改变编码块的块大小。 编码部分将传输数据转移到块编码处理以形成块编码数据。 调制部分调制块编码数据以形成数据符号; 并且排列（交织）部分以这样的方式布置（交织）块编码数据，使得包括它们各自的单个不同数据符号的编码块的块内编码数据在一起，然后提供所安排的（交织的 ）块编码数据到调制部分。 以这种方式，可以提供一种发射机装置，即使当调制多值的数量增加时，使用相对简单的结构来抑制突发错误，而不改变编码块的块大小。
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