公开(公告)号：US07420232B2

公开(公告)日：2008-09-02

申请号：US11402701

申请日：2006-04-11

申请人： Kazuhiro Fujikawa ,  Shin Harada ,  Kenichi Hirotsu ,  Satoshi Hatsukawa ,  Takashi Hoshino ,  Hiroyuki Matsunami ,  Tsunenobu Kimoto

发明人： Kazuhiro Fujikawa ,  Shin Harada ,  Kenichi Hirotsu ,  Satoshi Hatsukawa ,  Takashi Hoshino ,  Hiroyuki Matsunami ,  Tsunenobu Kimoto

IPC分类号： H01L29/80 ,  H01L31/112

CPC分类号： H01L29/0634 ,  H01L29/1058 ,  H01L29/1066 ,  H01L29/42316 ,  H01L29/66893 ,  H01L29/808

摘要： A lateral junction field effect transistor includes a first gate electrode layer arranged in a third semiconductor layer between source/drain region layers, having a lower surface extending on the second semiconductor layer, and doped with p-type impurities more heavily than the second semiconductor layer, and a second gate electrode layer arranged in a fifth semiconductor layer between the source/drain region layers, having a lower surface extending on a fourth semiconductor layer, having substantially the same concentration of p-type impurities as the first gate electrode layer, and having the same potential as the first gate electrode layer. Thereby, the lateral junction field effect transistor has a structure, which can reduce an on-resistance while maintaining good breakdown voltage properties.

摘要翻译： 横向结型场效应晶体管包括布置在源/漏区域之间的第三半导体层中的第一栅电极层，具有在第二半导体层上延伸的下表面，并且掺杂有比第二半导体层更重的p型杂质 以及布置在源极/漏极区域之间的第五半导体层中的第二栅极电极层，具有在第四半导体层上延伸的下表面，具有与第一栅极电极层基本相同的p型杂质浓度，以及 具有与第一栅极电极层相同的电位。 因此，横向结型场效应晶体管具有可以在保持良好的击穿电压特性的同时降低导通电阻的结构。

公开(公告)号：US20060118813A1

公开(公告)日：2006-06-08

申请号：US11337143

申请日：2006-01-20

申请人： Shin Harada ,  Kenichi Hirotsu ,  Hiroyuki Matsunami ,  Tsunenobu Kimoto

发明人： Shin Harada ,  Kenichi Hirotsu ,  Hiroyuki Matsunami ,  Tsunenobu Kimoto

IPC分类号： H01L31/111

CPC分类号： H01L29/808 ,  H01L29/0623 ,  H01L29/1066 ,  H01L29/1608

摘要： A lateral JFET has a basic structure including an n-type semiconductor layer (3) formed of an n-type impurity region and a p-type semiconductor layer formed of a p-type impurity region on the n-type semiconductor layer (3). Moreover, in the p-type semiconductor layer, there are provided a p+-type gate region layer (7) extending into the n-type semiconductor layer (3) and containing p-type impurities of an impurity concentration higher than that of the n-type semiconductor layer (3) and an n+-type drain region layer (9) spaced from the p+-type gate region layer (7) by a predetermined distance and containing n-type impurities of an impurity concentration higher than that of the n-type semiconductor layer (3). With this structure, the lateral JFET can be provided that has an ON resistance further decreased while maintaining a high breakdown voltage performance.

摘要翻译： 横向JFET具有包括由n型杂质区形成的n型半导体层（3）和在n型半导体层（3）上由p型杂质区形成的p型半导体层的基本结构， 。 此外，在p型半导体层中，设置延伸到n型半导体层（3）中并含有杂质的p型杂质的p +型栅极区域层（7） 浓度高于n型半导体层（3）的浓度以及与p + +型栅极区域层间隔开的n + + +型漏极区域（9） （7）预定距离并且包含杂质浓度高于n型半导体层（3）的杂质浓度的n型杂质。 利用这种结构，可以提供横向JFET，其具有进一步降低的导通电阻，同时保持高的击穿电压性能。

公开(公告)号：US06734461B1

公开(公告)日：2004-05-11

申请号：US10070472

申请日：2002-03-07

申请人： Hiromu Shiomi ,  Tsunenobu Kimoto ,  Hiroyuki Matsunami

发明人： Hiromu Shiomi ,  Tsunenobu Kimoto ,  Hiroyuki Matsunami

IPC分类号： H01L310312

CPC分类号： H01L29/1608 ,  C30B23/00 ,  C30B23/02 ,  C30B29/36 ,  H01L21/02378 ,  H01L21/02447 ,  H01L21/02516 ,  H01L21/02529 ,  H01L21/02579 ,  H01L21/02587 ,  H01L21/0262 ,  H01L21/02658 ,  H01L29/045 ,  H01L29/78

摘要： A SiC wafer comprises a 4H polytype SiC substrate 2 in which the crystal plane orientation is substantially {03-38}, and a buffer layer 4 composed of SiC formed over this SiC substrate 2. The {03-38} plane forms an angle of approximately 35° with respect to the axial direction in which micropipes and so forth extend, so micropipes and so forth are eliminated at the crystal sides, and do not go through to an active layer 6 on the buffer layer 4. Lattice mismatching between the SiC substrate 2 and the active layer 6 is suppressed by the buffer layer 4. Furthermore, anisotropy in the electron mobility is low because a 4H polytype is used. Therefore, it is possible to obtain a SiC wafer and a SiC semiconductor device with which there is little anisotropy in the electron mobility, and strain caused by lattice mismatching can be lessened, as well as a method for manufacturing these.

摘要翻译： SiC晶片包括其中晶体取向基本上为{03-38}的4H多型SiC衬底2，以及由该SiC衬底2上形成的由SiC构成的缓冲层4. {03-38}面形成 相对于其中微孔等的<0001>轴向延伸大约35°，因此在晶体侧消除了微管等，并且不会穿过缓冲层4上的有源层6。晶格不匹配 在SiC衬底2和有源层6之间被缓冲层4抑制。此外，由于使用4H多型，电子迁移率的各向异性低。 因此，可以获得在电子迁移率中几何异向性小的SiC晶片和SiC半导体器件，并且可以减小由晶格失配引起的应变以及其制造方法。

公开(公告)号：US20090315082A1

公开(公告)日：2009-12-24

申请号：US12552212

申请日：2009-09-01

申请人： Kazuhiro Fujikawa ,  Shin Harada ,  Kenichi Hirotsu ,  Satoshi Hatsukawa ,  Takashi Hoshino ,  Hiroyuki Matsunami ,  Tsunenobu Kimoto

发明人： Kazuhiro Fujikawa ,  Shin Harada ,  Kenichi Hirotsu ,  Satoshi Hatsukawa ,  Takashi Hoshino ,  Hiroyuki Matsunami ,  Tsunenobu Kimoto

IPC分类号： H01L29/808

CPC分类号： H01L29/0634 ,  H01L29/1058 ,  H01L29/1066 ,  H01L29/42316 ,  H01L29/66893 ,  H01L29/808

摘要： A lateral junction field effect transistor includes a first gate electrode layer arranged in a third semiconductor layer between source/drain region layers, having a lower surface extending on the second semiconductor layer, and doped with p-type impurities more heavily than the second semiconductor layer, and a second gate electrode layer arranged in a fifth semiconductor layer between the source/drain region layers, having a lower surface extending on a fourth semiconductor layer, having substantially the same concentration of p-type impurities as the first gate electrode layer, and having the same potential as the first gate electrode layer. Thereby, the lateral junction field effect transistor has a structure, which can reduce an on-resistance while maintaining good breakdown voltage properties.

摘要翻译： 横向结型场效应晶体管包括布置在源极/漏极区之间的第三半导体层中的第一栅电极层，具有在第二半导体层上延伸的下表面，并且掺杂有比第二半导体层更重的p型杂质 以及布置在源极/漏极区域之间的第五半导体层中的第二栅极电极层，具有在第四半导体层上延伸的下表面，具有与第一栅极电极层基本相同的p型杂质浓度，以及 具有与第一栅极电极层相同的电位。 因此，横向结型场效应晶体管具有可以在保持良好的击穿电压特性的同时降低导通电阻的结构。

公开(公告)号：US20060202238A1

公开(公告)日：2006-09-14

申请号：US11402701

申请日：2006-04-11

申请人： Kazuhiro Fujikawa ,  Shin Harada ,  Kenichi Hirotsu ,  Satoshi Hatsukawa ,  Takashi Hoshino ,  Hiroyuki Matsunami ,  Tsunenobu Kimoto

发明人： Kazuhiro Fujikawa ,  Shin Harada ,  Kenichi Hirotsu ,  Satoshi Hatsukawa ,  Takashi Hoshino ,  Hiroyuki Matsunami ,  Tsunenobu Kimoto

IPC分类号： H01L31/112

CPC分类号： H01L29/0634 ,  H01L29/1058 ,  H01L29/1066 ,  H01L29/42316 ,  H01L29/66893 ,  H01L29/808

摘要： A lateral junction field effect transistor includes a first gate electrode layer arranged in a third semiconductor layer between source/drain region layers, having a lower surface extending on the second semiconductor layer, and doped with p-type impurities more heavily than the second semiconductor layer, and a second gate electrode layer arranged in a fifth semiconductor layer between the source/drain region layers, having a lower surface extending on a fourth semiconductor layer, having substantially the same concentration of p-type impurities as the first gate electrode layer, and having the same potential as the first gate electrode layer. Thereby, the lateral junction field effect transistor has a structure, which can reduce an on-resistance while maintaining good breakdown voltage properties.

公开(公告)号：US07671387B2

公开(公告)日：2010-03-02

申请号：US12179320

申请日：2008-07-24

申请人： Kazuhiro Fujikawa ,  Shin Harada ,  Kenichi Hirotsu ,  Satoshi Hatsukawa ,  Takashi Hoshino ,  Hiroyuki Matsunami ,  Tsunenobu Kimoto

发明人： Kazuhiro Fujikawa ,  Shin Harada ,  Kenichi Hirotsu ,  Satoshi Hatsukawa ,  Takashi Hoshino ,  Hiroyuki Matsunami ,  Tsunenobu Kimoto

IPC分类号： H01L29/80

CPC分类号： H01L29/0634 ,  H01L29/1058 ,  H01L29/1066 ,  H01L29/42316 ,  H01L29/66893 ,  H01L29/808

摘要： A lateral junction field effect transistor includes a first gate electrode layer arranged in a third semiconductor layer between source/drain region layers, having a lower surface extending on the second semiconductor layer, and doped with p-type impurities more heavily than the second semiconductor layer, and a second gate electrode layer arranged in a fifth semiconductor layer between the source/drain region layers, having a lower surface extending on a fourth semiconductor layer, having substantially the same concentration of p-type impurities as the first gate electrode layer, and having the same potential as the first gate electrode layer. Thereby, the lateral junction field effect transistor has a structure, which can reduce an on-resistance while maintaining good breakdown voltage properties.

摘要翻译： 横向结型场效应晶体管包括布置在源/漏区域之间的第三半导体层中的第一栅电极层，具有在第二半导体层上延伸的下表面，并且掺杂有比第二半导体层更重的p型杂质 以及布置在源极/漏极区域之间的第五半导体层中的第二栅极电极层，具有在第四半导体层上延伸的下表面，具有与第一栅极电极层基本相同的p型杂质浓度，以及 具有与第一栅极电极层相同的电位。 因此，横向结型场效应晶体管具有可以在保持良好的击穿电压特性的同时降低导通电阻的结构。

公开(公告)号：US07528426B2

公开(公告)日：2009-05-05

申请号：US11337143

申请日：2006-01-20

申请人： Shin Harada ,  Kenichi Hirotsu ,  Hiroyuki Matsunami ,  Tsunenobu Kimoto

发明人： Shin Harada ,  Kenichi Hirotsu ,  Hiroyuki Matsunami ,  Tsunenobu Kimoto

IPC分类号： H01L29/808

CPC分类号： H01L29/808 ,  H01L29/0623 ,  H01L29/1066 ,  H01L29/1608

摘要： A lateral JFET has a basic structure including an n-type semiconductor layer (3) formed of an n-type impurity region and a p-type semiconductor layer formed of a p-type impurity region on the n-type semiconductor layer (3). Moreover, in the p-type semiconductor layer, there are provided a p+-type gate region layer (7) extending into the n-type semiconductor layer (3) and containing p-type impurities of an impurity concentration higher than that of the n-type semiconductor layer (3) and an n+-type drain region layer (9) spaced from the p+-type gate region layer (7) by a predetermined distance and containing n-type impurities of an impurity concentration higher than that of the n-type semiconductor layer (3). With this structure, the lateral JFET can be provided that has an ON resistance further decreased while maintaining a high breakdown voltage performance.

摘要翻译： 横向JFET具有包括由n型杂质区形成的n型半导体层（3）和在n型半导体层（3）上由p型杂质区形成的p型半导体层的基本结构， 。 此外，在p型半导体层中，设置有延伸到n型半导体层（3）中的p +型栅极区域（7），并且含有比n的杂质浓度高的p型杂质 型半导体层（3）和与p +型栅极区域（7）间隔预定距离的n +型漏极区域（9），并且含有杂质浓度高于n的n型杂质 型半导体层（3）。 利用这种结构，可以提供横向JFET，其具有进一步降低的导通电阻，同时保持高的击穿电压性能。

公开(公告)号：US07321142B2

公开(公告)日：2008-01-22

申请号：US10544017

申请日：2004-05-21

申请人： Kazuhiro Fujikawa ,  Shin Harada ,  Hiroyuki Matsunami ,  Tsunenobu Kimoto

发明人： Kazuhiro Fujikawa ,  Shin Harada ,  Hiroyuki Matsunami ,  Tsunenobu Kimoto

IPC分类号： H01L29/80

CPC分类号： H01L29/66901 ,  H01L29/0634 ,  H01L29/1608 ,  H01L29/808

摘要： On an SiC single crystal substrate, an electric field relaxation layer and a p− type buffer layer are formed. The electric field relaxation layer is formed between the p− type buffer layer and the SiC single crystal substrate to contact SiC single crystal substrate. On the p− type buffer layer, an n type semiconductor layer is formed. On the n type semiconductor layer, a p type semiconductor layer is formed. In the p type semiconductor layer, an n+ type source region layer and an n+ type drain region layer are formed separated by a prescribed distance from each other. At a part of the region of p type semiconductor layer between the n+ type source region layer and the n+ type drain region layer, a p+ type gate region layer is formed.

摘要翻译： 在SiC单晶衬底上形成电场弛豫层和p型缓冲层。 在p-型缓冲层和SiC单晶衬底之间形成电场弛豫层以接触SiC单晶衬底。 在p型缓冲层上形成n型半导体层。 在n型半导体层上形成p型半导体层。 在p型半导体层中，形成n +型源极区域和n +型漏极区域彼此分开规定的距离。 在n +型源极区域和n +型漏极区域之间的p型半导体层的区域的一部分，形成p +型栅极区域层。

公开(公告)号：US20060113574A1

公开(公告)日：2006-06-01

申请号：US10544017

申请日：2004-05-21

申请人： Kazuhiro Fujikawa ,  Shin Harada ,  Hiroyuki Matsunami ,  Tsunenobu Kimoto

发明人： Kazuhiro Fujikawa ,  Shin Harada ,  Hiroyuki Matsunami ,  Tsunenobu Kimoto

IPC分类号： H01L29/80

CPC分类号： H01L29/66901 ,  H01L29/0634 ,  H01L29/1608 ,  H01L29/808

摘要： On an SiC single crystal substrate, an electric field relaxation layer and a p− type buffer layer are formed. The electric field relaxation layer is formed between the p− type buffer layer and the SiC single crystal substrate to contact SiC single crystal substrate. On the p− type buffer layer, an n type semiconductor layer is formed. On the n type semiconductor layer, a p type semiconductor layer is formed. In the p type semiconductor layer, an n+ type source region layer and an n+ type drain region layer are formed separated by a prescribed distance from each other. At a part of the region of p type semiconductor layer between the n+ type source region layer and the n+ type drain region layer, a p+ type gate region layer is formed.

摘要翻译： 在SiC单晶衬底上形成电场弛豫层和p型缓冲层。 在p-型缓冲层和SiC单晶衬底之间形成电场弛豫层以接触SiC单晶衬底。 在p型缓冲层上形成n型半导体层。 在n型半导体层上形成p型半导体层。 在p型半导体层中，形成n +型源极区域和n +型漏极区域彼此分开规定的距离。 在n +型源极区域和n +型漏极区域之间的p型半导体层的区域的一部分，形成p +型栅极区域层。

公开(公告)号：US07049644B2

公开(公告)日：2006-05-23

申请号：US10496040

申请日：2002-12-02

申请人： Kazuhiro Fujikawa ,  Shin Harada ,  Kenichi Hirotsu ,  Satoshi Hatsukawa ,  Takashi Hoshino ,  Hiroyuki Matsunami ,  Tsunenobu Kimoto

发明人： Kazuhiro Fujikawa ,  Shin Harada ,  Kenichi Hirotsu ,  Satoshi Hatsukawa ,  Takashi Hoshino ,  Hiroyuki Matsunami ,  Tsunenobu Kimoto

IPC分类号： H01L29/80 ,  H01L31/112

CPC分类号： H01L29/0634 ,  H01L29/1058 ,  H01L29/1066 ,  H01L29/42316 ,  H01L29/66893 ,  H01L29/808

摘要： A lateral junction field effect transistor includes a first gate electrode layer arranged in a third semiconductor layer between source/drain region layers, having a lower surface extending on the second semiconductor layer, and doped with p-type impurities more heavily than the second semiconductor layer, and a second gate electrode layer arranged in a fifth semiconductor layer between the source/drain region layers, having a lower surface extending on a fourth semiconductor layer, having substantially the same concentration of p-type impurities as the first gate electrode layer, and having the same potential as the first gate electrode layer. Thereby, the lateral junction field effect transistor has a structure, which can reduce an on-resistance while maintaining good breakdown voltage properties.

摘要翻译： 横向结型场效应晶体管包括布置在源/漏区域之间的第三半导体层中的第一栅电极层，具有在第二半导体层上延伸的下表面，并且掺杂有比第二半导体层更重的p型杂质 以及布置在源极/漏极区域之间的第五半导体层中的第二栅极电极层，具有在第四半导体层上延伸的下表面，具有与第一栅极电极层基本相同的p型杂质浓度，以及 具有与第一栅极电极层相同的电位。 因此，横向结型场效应晶体管具有可以在保持良好的击穿电压特性的同时降低导通电阻的结构。