公开(公告)号：US6002861A

公开(公告)日：1999-12-14

申请号：US113628

申请日：1998-07-10

Applicant: Michael R. Butts ,  Jon A. Batcheller

Inventor： Michael R. Butts ,  Jon A. Batcheller

IPC: G06F17/50 ,  H03K17/693 ,  H03K17/735

CPC classification number: G06F17/5027

Abstract: A plurality of electronically reconfigurable gate array (ERCGA) logic chips are interconnected via a reconfigurable interconnect, and electronic representations of large digital networks are converted to take temporary actual operating hardware form on the interconnected chips. The reconfigurable interconnect permits the digital network realized on the interconnected chips to be changed at will, making the system well suited for a variety of purposes including simulation, prototyping, execution and computing. The reconfigurable interconnect may comprise a partial crossbar that is formed of ERCGA chips dedicated to interconnection functions, wherein each such interconnect ERCGA is connected to at least one, but not all of the pins of a plurality of the logic chips. Other reconfigurable interconnect topologies are also detailed.

Abstract translation: 多个电子可重构门阵列（ERCGA）逻辑芯片经由可重配置互连互连，并且大数字网络的电子表示被转换为在互连芯片上采取暂时的实际操作硬件形式。 可重构互连允许在互连芯片上实现的数字网络随意改变，使系统非常适合于各种目的，包括仿真，原型设计，执行和计算。 可重配置互连可以包括由专用于互连功能的ERCGA芯片形成的部分交叉开关，其中每个这样的互连ERCGA连接到多个逻辑芯片的至少一个但不是全部的引脚。 其他可重配置互连拓扑也是详细的。

公开(公告)号：US5970240A

公开(公告)日：1999-10-19

申请号：US883025

申请日：1997-06-25

Applicant: Tao Shinn Chen ,  Dam Van Bui

Inventor： Tao Shinn Chen ,  Dam Van Bui

IPC: G06F12/02 ,  G06F9/44

CPC classification number: G06F12/0292

Abstract: A configurable method and apparatus for implementing the various large memory instances commonly found in a user's design in a hardware logic emulation system is disclosed. No external boards or systems are required to implement typical memory instances. The method and apparatus sorts the memory instances in the user's input design, packing as many memory instances as possible into a physical RAM on the emulation boards. The method also counts the number of physical RAMs necessary to implement the plurality of memory instances. The method maps the memory instances into physical RAMs, and routes the address, data and control signals and controller circuit into a programmable logic chip.

Abstract translation: 公开了一种用于实现硬件逻辑仿真系统中用户设计中通常发现的各种大型存储器实例的可配置方法和装置。 不需要外部板或系统来实现典型的内存实例。 该方法和装置对用户输入设计中的存储器实例进行排序，将尽可能多的存储器实例打包到仿真板上的物理RAM中。 该方法还计数实现多个存储器实例所需的物理RAM的数量。 该方法将存储器实例映射到物理RAM中，并将地址，数据和控制信号以及控制器电路路由到可编程逻辑芯片中。

公开(公告)号：US5887158A

公开(公告)日：1999-03-23

申请号：US825967

申请日：1997-04-04

Applicant: Stephen P. Sample ,  Terry L. Goode

Inventor： Stephen P. Sample ,  Terry L. Goode

IPC: H01R9/22 ,  G06F17/50 ,  H05K1/14 ,  H05K7/10 ,  H05K7/14 ,  G06F9/455

CPC classification number: H05K7/1445 ,  H05K1/14 ,  H05K2201/044

Abstract: A physical interconnection architecture for making connections between a plurality of first printed-circuit boards and a plurality of second printed-circuit boards includes a midplane printed-circuit board having a plurality of first connectors oriented in a first direction on one side of the midplane for making connections to the plurality of first printed-circuit boards. The midplane printed-circuit board also has a plurality of second connectors oriented in a second direction orthogonal to the plurality of first connectors on the other side of the midplane. The connectors are positioned such that connection pins on the plurality of first connectors and plurality of second connectors in regions of intersection are double-ended pins common to both. The remaining connection pins of the plurality of first connectors are single-ended connection pins which are connected to the single-ended connection pins of the plurality of second connectors via conductive traces on the midplane printed-circuit board.

Abstract translation: 用于在多个第一印刷电路板和多个第二印刷电路板之间进行连接的物理互连架构包括：中平面印刷电路板，其具有在中平面的一侧上沿第一方向取向的多个第一连接器， 连接到所述多个第一印刷电路板。 中平面印刷电路板还具有多个第二连接器，其在与中平面的另一侧上的多个第一连接器正交的第二方向上定向。 连接器被定位成使得多个第一连接器上的连接销和交叉区域中的多个第二连接器是两者共同的双端销。 多个第一连接器的其余连接引脚是单端连接引脚，其通过中平面印刷电路板上的导电迹线连接到多个第二连接器的单端连接引脚。

公开(公告)号：US5819065A

公开(公告)日：1998-10-06

申请号：US597197

申请日：1996-02-06

Applicant: John E. Chilton ,  Tony R. Sarno ,  Ingo Schaefer

Inventor： John E. Chilton ,  Tony R. Sarno ,  Ingo Schaefer

IPC: G06F11/22 ,  G06F11/26 ,  G06F17/50 ,  G06F9/455

CPC classification number: G06F11/261 ,  G06F17/5027

Abstract: A system and method for emulating memory designs is described. The system includes a time sliced logic emulator. The time sliced logic emulator emulates the functions performed in one cycle of a target design by emulating portions of the functions in a set of time slices. That is, a set of time slices represents a single clock cycle in the target design. The system emulates many different types of memory designs included in the target design. The system includes an emulation memory. The memory designs are mapped to the emulation memory via a programmable address generation block. For a given time slice, the programmable address generation block generates an address that maps all or part of a memory design address to an emulation memory address. The programmable address generation block allows multiple memory designs to be mapped to a single emulation memory and allows a single memory design to be mapped to multiple emulation memories. Thus, over multiple time slices, the system can emulate many different types of memories.

Abstract translation: 描述了用于模拟存储器设计的系统和方法。 该系统包括时间分片逻辑仿真器。 时间分片逻辑仿真器通过模拟一组时间片中的部分功能来模拟在目标设计的一个周期中执行的功能。 也就是说，一组时间片表示目标设计中的单个时钟周期。 该系统模拟目标设计中包含的许多不同类型的存储器设计。 该系统包括一个仿真存储器。 存储器设计通过可编程地址生成块映射到仿真存储器。 对于给定的时间片，可编程地址生成块产生将存储器设计地址的全部或部分映射到仿真存储器地址的地址。 可编程地址生成块允许将多个存储器设计映射到单个仿真存储器，并允许将单个存储器设计映射到多个仿真存储器。 因此，在多个时间片上，系统可以模拟许多不同类型的存储器。

公开(公告)号：US5715172A

公开(公告)日：1998-02-03

申请号：US638309

申请日：1996-04-26

Applicant: Ping-San Tzeng

Inventor： Ping-San Tzeng

IPC: G01R31/28 ,  G01R31/00 ,  G06F1/06 ,  G06F1/08 ,  G06F11/22 ,  G06F17/50 ,  G06F15/00

CPC classification number: G06F17/5027 ,  G06F1/06 ,  G06F1/08 ,  G06F17/5031 ,  G06F17/5045 ,  G06F17/5054

Abstract: A method of identifying potential clock qualifiers in netlist description of an integrated circuit, the netlist comprising logic elements. The method comprises the steps of initializing every net of the netlist to a speed of zero, identifying all potential clock nets so that all signals with a path to a clock source has a speed of one, computing the maximum speed of each output net of each of the logic elements in the netlist, and marking as a potential clock qualifier any net of the netlist that is input to the logic elements in the netlist that is slower than the maximum speed of any net that is input to the logic elements.

Abstract translation: 一种在集成电路的网表描述中识别潜在时钟限定符的方法，所述网表包括逻辑元件。 该方法包括以下步骤：将网表的每个网络初始化为零速度，识别所有潜在的时钟网络，使得具有到时钟源的路径的所有信号的速度为1，计算每个输出网络的每个输出网络的最大速度 的网表中的逻辑元素，并且将网表中的逻辑元素的任何净网标记为潜在的时钟限定器，该网表比输入到逻辑元件的任何网络的最大速度慢。

公开(公告)号：US5475830A

公开(公告)日：1995-12-12

申请号：US829181

申请日：1992-01-31

Applicant: Nang-Ping Chen ,  Robert J. Ko ,  Jeong-Tyng Li ,  Thomas B. Huang ,  Ming-Yang Wang

Inventor： Nang-Ping Chen ,  Robert J. Ko ,  Jeong-Tyng Li ,  Thomas B. Huang ,  Ming-Yang Wang

IPC: G06F1/10 ,  A21B1/24 ,  F24C15/32 ,  G06F1/12 ,  G06F11/26 ,  G06F17/50 ,  H01L21/82 ,  H03K19/177 ,  G06F9/455

CPC classification number: A21B1/245 ,  G06F17/5027 ,  G06F17/5054

Abstract: A method and a structure for implementing integrated circuit designs into a plurality of clocked and unclocked reprogrammable logic circuits. Software structures analyze the target logic circuit, form clusters, partition the integrated circuit design and implement the partitions into the clocked and unclocked reprogrammable logic circuits in order to prevent hold time violation artifacts.

Abstract translation: 一种用于将集成电路设计实现为多个时钟和非锁定的可再编程逻辑电路的方法和结构。 软件结构分析目标逻辑电路，形成集群，分割集成电路设计，并将分区实现为时钟和未锁定的可编程逻辑电路，以防止保持时间违规伪像。

公开(公告)号：US20090259458A1

公开(公告)日：2009-10-15

申请号：US12491106

申请日：2009-06-24

Applicant: Alexandre Birguer

Inventor： Alexandre Birguer

IPC: G06F9/455 ,  G06F12/06

CPC classification number: G06F12/1072 ,  G06F17/5027

Abstract: A memory mapping system for providing compact mapping between dissimilar memory systems and methods for manufacturing and using same. The memory mapping system can compactly map contents from one or more first memory systems into a second memory system without a loss of memory space in the second memory system. Advantageously, the memory mapping system can be applied to hardware emulator memory systems to more efficiently map design memory systems into an emulation memory system during compilation.

Abstract translation: 一种用于在不同的存储器系统之间提供紧密映射的存储器映射系统以及用于制造和使用它们的方法。 存储器映射系统可以将内容从一个或多个第一存储器系统紧凑地映射到第二存储器系统中，而不会损失第二存储器系统中的存储器空间。 有利地，存储器映射系统可以应用于硬件仿真器存储器系统，以在编译期间将设计存储器系统更有效地映射到仿真存储器系统中。

公开(公告)号：US07440884B2

公开(公告)日：2008-10-21

申请号：US10373558

申请日：2003-02-24

Applicant: Platon Beletsky ,  Alon Kfir ,  Tsair-Chin Lin

Inventor： Platon Beletsky ,  Alon Kfir ,  Tsair-Chin Lin

IPC: G06F9/455

CPC classification number: G06F17/5027

Abstract: A method and apparatus for debugging circuit designs having random access memory therein. The circuit design is emulated on a hardware logic emulator. The RAM emulated by the emulator can be rewound to a previous state, and then replayed. The RAM emulated by the emulator can also be reconstructed to a state the RAM maintained at some point during a trace window.

Abstract translation: 一种用于调试其中具有随机存取存储器的电路设计的方法和装置。 电路设计在硬件逻辑仿真器上仿真。 由仿真器模拟的RAM可以重绕到先前的状态，然后重播。 由仿真器仿真的RAM也可以被重建为在跟踪窗口期间某个时刻保持RAM的状态。

公开(公告)号：US07379861B2

公开(公告)日：2008-05-27

申请号：US11133819

申请日：2005-05-19

Applicant: Alon Kfir ,  Viktor Salitrennik

Inventor： Alon Kfir ,  Viktor Salitrennik

IPC: G06F9/455

CPC classification number: G06F17/5027

Abstract: An improved emulation system having an improved trigger mechanism is disclosed. During the compilation of the circuit design, a portion of the emulation resources are reserved for dynamic netlists. The dynamic netlists allows a user to create arbitrary trigger circuits that can be based on any signal generated by the device under test during run time, including signals that were optimized out of the design during the compilation process. The dynamic netlists can be loaded and used in the emulator without having to recompile the entire design, which could take many hours. This enables a user to quickly and efficiently debug circuit designs.

Abstract translation: 公开了一种具有改进的触发机构的改进的仿真系统。 在编译电路设计期间，一部分仿真资源被保留给动态网表。 动态网表允许用户创建任意的触发电路，其可以基于在运行期间由被测器件产生的任何信号，包括在编译过程中优化设计的信号。 可以在仿真器中加载和使用动态网表，而无需重新编译整个设计，这可能需要很多时间。 这使得用户能够快速有效地调试电路设计。

公开(公告)号：US20050267732A1

公开(公告)日：2005-12-01

申请号：US11047802

申请日：2005-01-31

Applicant: William Beausoleil ,  Lawrence Thomas ,  Arthur Sarkisian ,  Beshara Elmufdi

Inventor： William Beausoleil ,  Lawrence Thomas ,  Arthur Sarkisian ,  Beshara Elmufdi

IPC: G06F9/455 ,  G06F17/50

CPC classification number: G06F17/5027

Abstract: A processor-based emulation system for emulating an integrated circuit design, the processor-based emulation system including emulation circuitry and capture circuitry. The capture circuitry is operable to capture processing results from the emulation circuitry. The captured processing results can be used to identify functional errors in the integrated circuit design. Because the processor-based emulation system includes capture circuitry, emulation circuitry is not used for capturing the processing results.

Abstract translation: 用于仿真集成电路设计的基于处理器的仿真系统，包括仿真电路和捕获电路的基于处理器的仿真系统。 捕获电路可操作以捕获来自仿真电路的处理结果。 捕获的处理结果可用于识别集成电路设计中的功能错误。 由于基于处理器的仿真系统包括捕获电路，仿真电路不用于捕获处理结果。