公开(公告)号：US07489780B2

公开(公告)日：2009-02-10

申请号：US10818753

申请日：2004-04-06

Applicant: Andrew Dellow ,  Rodgrigo Cordero

Inventor： Andrew Dellow ,  Rodgrigo Cordero

IPC: H04L9/00

CPC classification number: H04N21/42623 ,  G06F21/10 ,  H04N7/165 ,  H04N21/4405 ,  H04N21/4623

Abstract: A semiconductor integrated circuit for the processing of conditional access television signals comprises an input interface for receiving encrypted television signals and an output interface for output of decrypted television signals. Control signals broadcast with the television signals include control words and common keys. Entitlement messages are received in encrypted form, encrypted according to a secret key unique to each semiconductor integrated circuit. The input interface is connected to a decryption circuit whereby the only manner of providing the common keys to the circuit are in encrypted form encrypted according to the secret key. Due to the monolithic nature of the circuit, no secrets are exposed and the system is secure. Alternatively, the entitlement messages are encrypted for decryption with the common keys and a unique ID stored in the circuit is compared with an ID in a received entitlement message. Only if the received and stored IDs match can the rights be stored and used.

Abstract translation: 用于处理条件接收电视信号的半导体集成电路包括用于接收加密的电视信号的输入接口和用于输出解密的电视信号的输出接口。 用电视信号广播的控制信号包括控制字和公共密钥。 以加密形式接收授权消息，根据每个半导体集成电路特有的秘密密钥进行加密。 输入接口连接到解密电路，由此向电路提供公共密钥的唯一方式是根据密钥加密的加密形式。 由于电路的整体性质，没有暴露的秘密和系统是安全的。 或者，授权消息被加密以用公共密钥进行解密，并且存储在电路中的唯一ID与接收到的授权消息中的ID进行比较。 只有收到和存储的ID匹配才能保存和使用权限。

公开(公告)号：US07392171B2

公开(公告)日：2008-06-24

申请号：US10603055

申请日：2003-06-24

Applicant: Gianluca Blasi ,  Reenee Tayal

Inventor： Gianluca Blasi ,  Reenee Tayal

IPC: G06F17/50

CPC classification number: G06F17/5022 ,  Y10S707/99933

Abstract: A computer based test bench generator (1) for verifying integrated circuits specified by models in a Hardware Description Language includes a repository (10) storing a general set of self-checking tests applicable to the integrated circuits. A capability is provided for entering behavior data (21) of an integrated circuit model (20), and for entering configuration data (22) of the integrated circuit model. The generator automatically generates test benches (30) in the Hardware Description Language by making a selection and setup of suitable tests from the repository according to the specified integrated circuit model, configuration and behavior data.

Abstract translation: 用于验证由硬件描述语言中的模型指定的集成电路的基于计算机的测试台发生器（1）包括存储适用于集成电路的一般的一组自检测试的存储库（10）。 提供了用于输入集成电路模型（20）的行为数据（21）和用于输入集成电路模型的配置数据（22）的能力。 发电机通过根据指定的集成电路模型，配置和行为数据从存储库进行选择和设置合适的测试，自动生成硬件描述语言中的测试台（30）。

公开(公告)号：US07391909B2

公开(公告)日：2008-06-24

申请号：US10159954

申请日：2002-05-31

Applicant: Victor Robert Watson

Inventor： Victor Robert Watson

IPC: G06K9/36

CPC classification number: H04N19/86 ,  H04N19/42 ,  H04N19/423 ,  H04N19/61

Abstract: A method for performing a reordering operation on a matrix of input data values, the method comprising: loading the data values into a computer store by forming a plurality of data strings, each data string comprising a plurality of data sub-strings and each data sub-string representing at least one of the data values, and storing each data string in a register of the computer store in which its sub-strings are not individually addressable; and performing a series of data reordering steps operating on one or more of said data strings to reorder said data values; the reordering operation being a scan-wise reordering operation.

Abstract translation: 一种用于对输入数据值的矩阵执行重排序操作的方法，所述方法包括：通过形成多个数据串将数据值加载到计算机存储器中，每个数据串包括多个数据子串和每个数据子 - 字符串表示数据值中的至少一个，并将每个数据串存储在其子串不能单独寻址的计算机存储的寄存器中; 以及执行对一个或多个所述数据串进行操作的一系列数据重排序步骤，以重新排列所述数据值; 重排序操作是扫描式重排序操作。

公开(公告)号：US07372906B2

公开(公告)日：2008-05-13

申请号：US10391442

申请日：2003-03-17

Applicant: Martin Bolton

Inventor： Martin Bolton

IPC: H04N7/12 ,  H04N11/02 ,  H04N11/04 ,  H04B1/66

CPC classification number: H04N19/42 ,  H04N19/126 ,  H04N19/13 ,  H04N19/137 ,  H04N19/15 ,  H04N19/172 ,  H04N19/176 ,  H04N19/61 ,  H04N19/91

Abstract: Data is discrete cosine transformed and streamed to a processor where quantized and inverse quantized blocks are generated. A second streaming data connection streams the inverse quantized blocks to an inverse discrete cosine transform block to generate reconstructed prediction error macroblocks. An addition circuit adds each reconstructed prediction error macroblock and its corresponding predictor macroblock to generate a respective reconstructed macroblock. The quantized macroblocks are zig-zag scanned, run level coded and variable length coded to generate and encoded bitstream.

Abstract translation: 数据是离散余弦变换并流式传输到产生量化和反量化块的处理器。 第二流数据连接将反量化块流向逆离散余弦变换块，以产生重建的预测误差宏块。 加法电路将每个重建的预测误差宏块及其对应的预测器宏块相加以生成相应的重建宏块。 量化的宏块是锯齿形扫描，运行级编码和可变长度编码以生成和编码比特流。

公开(公告)号：US07325018B2

公开(公告)日：2008-01-29

申请号：US09769004

申请日：2001-01-24

Applicant: David Smith

Inventor： David Smith

IPC: G06F17/30

CPC classification number: G06F17/50 ,  G06F17/30067 ,  Y10S707/99953 ,  Y10S707/99954

Abstract: A method is disclosed for operating a computer system in order to validate data stored in a plurality of data files in a database. Each of the data files have an associated file type and are arranged in a plurality of data stores in the database. At least one of the data files is a data dependent file which contains data dependent upon data in one or more other files of the data store. The method includes the steps of selecting a file locator which is associated with a respective one data store in the database, via the selected file locator identifying a first dependent file and identifying one or more other files on which said first file is dependent. For each identified file a first file reader is selected which is associated with the file type of the identified file. Via each selected first file reader a predetermined parameter of the identified file is determined. The method further includes the steps of comparing the predetermined parameter from the first file with that from the or each other file and responsive to the comparison step providing an output signal for each data file indicating whether the data file is valid.

Abstract translation: 公开了一种用于操作计算机系统以便验证存储在数据库中的多个数据文件中的数据的方法。 每个数据文件具有相关联的文件类型并且被排列在数据库中的多个数据存储器中。 数据文件中的至少一个是依赖于数据的文件，该文件包含取决于数据存储的一个或多个其他文件中的数据的数据。 该方法包括以下步骤：经由所选择的文件定位器选择与数据库中相应的一个数据存储相关联的文件定位器，该文件定位器识别第一依赖文件并识别所述第一文件依赖于其上的一个或多个其他文件。 对于每个识别的文件，选择与识别的文件的文件类型相关联的第一文件读取器。 通过每个选择的第一文件读取器，确定所识别的文件的预定参数。 该方法还包括以下步骤：将来自第一文件的预定参数与来自第一文件的预定参数进行比较，并响应于比较步骤，为每个数据文件提供指示数据文件是否有效的输出信号。

公开(公告)号：US20070280475A1

公开(公告)日：2007-12-06

申请号：US10583577

申请日：2004-12-17

Applicant: Andrew Dellow ,  Howard Gurney

Inventor： Andrew Dellow ,  Howard Gurney

IPC: H04K1/10

CPC classification number: G06F21/72 ,  G06F12/1408 ,  G06F21/79 ,  G06F21/85

Abstract: A monolithic semiconductor integrated circuit is provided for selectively encrypting or decrypting data transmitted between one of a plurality of devices on the circuit and an external memory. Two series of data pathways connect the devices and the external memory. The first series of data pathways passes through a cryptographic circuit causing data to be encrypted or decrypted, and the other series of data pathways provides an unhindered route. When a data access request is made by a device, the data is selectively routed along one of the two series of data pathways according to the identification of the device making the data access request. In one example, if data is transmitted from a device to the external memory, the data is selectively encrypted before being stored in the external memory if the device transmitting the data is identified as secure. Then, when that data is retrieved from the external memory by a second device, the data is selectively decrypted only if the second device is identified as secure.

Abstract translation: 提供单片半导体集成电路，用于选择性地加密或解密在电路上的多个设备之一和外部存储器之间传输的数据。 两组数据通路连接设备和外部存储器。 数据路径的第一系列通过加密电路，导致数据被加密或解密，另一系列的数据路径提供了一个不受阻碍的路由。 当设备进行数据访问请求时，根据进行数据访问请求的设备的标识，数据沿着两个数据路径中的一个选择性地路由选择。 在一个示例中，如果数据从设备发送到外部存储器，则如果发送数据的设备被识别为安全的，则在被存储在外部存储器中之前，数据被选择性地加密。 然后，当通过第二设备从外部存储器检索数据时，只有当第二设备被识别为安全时才选择性地解密该数据。

公开(公告)号：US20070200960A1

公开(公告)日：2007-08-30

申请号：US10575650

申请日：2003-10-16

Applicant: Peter Bennett ,  Paul Elliott ,  Andrew Dellow

Inventor： Peter Bennett ,  Paul Elliott ,  Andrew Dellow

IPC: H04N5/38

CPC classification number: H04N21/44 ,  H04N7/165 ,  H04N21/26606 ,  H04N21/42623 ,  H04N21/6334

Abstract: A semiconductor integrated circuit for the processing of conditional access television signals that includes an input interface for receiving encrypted television signals and an output interface for output of decrypted television signals. The semiconductor integrated circuit is provided with some functionality restricted in some way by preventing one or more hardware circuit elements from operating, such as an MPEG decoder, display engine, IO ports or main CPU. To enable the functionality, a subscriber must pay for a service and then receives an encrypted message broadcast to the semiconductor integrated circuit that is decrypted and instructs functionality to be turned on or off.

Abstract translation: 一种用于处理条件接收电视信号的半导体集成电路，包括用于接收加密的电视信号的输入接口和用于输出解密的电视信号的输出接口。 半导体集成电路具有通过防止一个或多个硬件电路元件操作（例如MPEG解码器，显示引擎，IO端口或主CPU）以某种方式受到限制的某些功能。 为了实现该功能，用户必须支付服务费用，然后接收加密的消息广播到被解密的半导体集成电路，并指示功能被打开或关闭。

公开(公告)号：US20070160151A1

公开(公告)日：2007-07-12

申请号：US10580762

申请日：2004-11-23

Applicant: Martin Bolton ,  Michele Carrano

Inventor： Martin Bolton ,  Michele Carrano

IPC: H04N11/02 ,  H04N7/12

CPC classification number: H04N7/24 ,  H04N19/42

Abstract: A video decoding circuit comprising: a first video data processor; a second video data processor; and a connection connecting the first video data processor and the second data processor; wherein the first video data processor is arranged to receive a first signal comprising encoded video data, process the first signal to provide a second signal and output the second signal. The first video data processor being arranged to process the first signal dependent on at least part of the received first signal. The second video data processor is arranged to receive at least a part of the second signal, process the at least a part of the second signal to provide a third signal, and output the third signal, the second and third signals comprising a decoded video image stream. The second video data processor is arranged to process the at least part of the second signal dependent on at least part of the at least part of second signal.

Abstract translation: 一种视频解码电路，包括：第一视频数据处理器; 第二视频数据处理器; 以及连接第一视频数据处理器和第二数据处理器的连接; 其中所述第一视频数据处理器被布置为接收包括编码视频数据的第一信号，处理所述第一信号以提供第二信号并输出​​所述第二信号。 第一视频数据处理器被配置为根据接收的第一信号的至少一部分来处理第一信号。 第二视频数据处理器被布置成接收第二信号的至少一部分，处理第二信号的至少一部分以提供第三信号，并输出第三信号，第二和第三信号包括解码视频图像 流。 第二视频数据处理器被配置为根据第二信号的至少部分的至少一部分来处理第二信号的至少一部分。

公开(公告)号：US07216342B2

公开(公告)日：2007-05-08

申请号：US10099455

申请日：2002-03-14

Applicant: Trefor Southwell ,  Peter Hedinger

Inventor： Trefor Southwell ,  Peter Hedinger

IPC: G06F9/44

CPC classification number: G06F12/126 ,  G06F8/54

Abstract: A method of linking a plurality of object files to generate an executable program, the method comprises identifying in the object files at least one routine to be locked into a cache when the program is executed, locating said routine at a set of memory addresses which man onto a set of cache locations and introducing into the executable program gaps at other sets of memory addresses which map onto the same set of cache locations.

Abstract translation: 一种链接多个对象文件以生成可执行程序的方法，所述方法包括在执行程序时在目标文件中识别要被锁定到高速缓存中的至少一个例程，将所述例程定位在一组存储器地址 到一组缓存位置，并将映射到同一组高速缓存位置的其他存储器地址集合引入可执行程序间隙。

公开(公告)号：US07174357B2

公开(公告)日：2007-02-06

申请号：US10291850

申请日：2002-11-08

Applicant: Tariq Kurd

Inventor： Tariq Kurd

IPC: G06F7/52 ,  G06F7/38

CPC classification number: G06F7/535 ,  G06F7/483 ,  G06F7/4873 ,  G06F7/5375 ,  G06F7/5525 ,  G06F2207/5528

Abstract: Circuitry for carrying out an arithmetic operation requiring a plurality of iterations, such as division or square root operations, utilizes N sets of iteration circuitry arranged one after the other so that at least one of the sets of iteration circuitry receives an output from a preceding one of the sets of iteration circuitry. Each of the sets of iteration circuitry includes at least one adder part, wherein a full adder is provided by at least one part in one of the sets of iteration circuitry and a second part in a succeeding one of the sets of iteration circuitry.

Abstract translation: 用于执行需要多次迭代（诸如除法或平方根操作）的算术运算的电路利用一个接一个地布置的N组迭代电路，使得迭代电路组中的至少一个接收来自前一个的输出 的迭代电路组。 迭代电路集合中的每一个包括至少一个加法器部分，其中全加器由迭代电路组之一中的至少一个部分提供，并且迭代电路组中的后一组中的第二部分。