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公开(公告)号：US4094136A
公开(公告)日：1978-06-13
申请号：US753129
申请日：1976-12-22
申请人： Hitomi Aizawa
发明人： Hitomi Aizawa
摘要： An inspection circuit for facilitating the inspection of the components of an electronic timepiece at the time that same is manufactured is provided. The inspection circuit is provided in an electronic timepiece having oscillator circuitry for producing high frequency time standard signals and divider circuitry for dividing down the high frequency time standard signal and producing a lower frequency time standard signal. The electronic timepiece further includes timekeeping counter circuitry for producing timekeeping signals and a digital display for displaying time in response to the timekeeping signals being applied thereto. The inspection circuit of the instant invention is particularly characterized by an auto-clear circuit coupled to the timekeeping counter and divider circuitry for detecting a power-on condition and in response thereto, applying a reset signal to the divider and timekeeping counter circuitry to thereby reset the counts thereof. The inspection circuit is coupled intermediate the divider timekeeping counter and divider circuitry and is adapted to receive the reset signal and apply to the digital display a first inspection signal to permit a first inspection of the digital display to be effected until the flower frequency time standard signal is applied to the inspection circuit.
摘要翻译： 提供了一种便于在制造同一时间检查电子表的部件的检查电路。 检查电路设置在具有用于产生高频时间标准信号的振荡器电路和用于分频高频时间标准信号并产生较低频率时间标准信号的分频器电路的电子表中。 电子钟表还包括用于产生计时信号的计时计数器电路和用于响应于应用计时信号而显示时间的数字显示器。 本发明的检查电路的特征在于，自动清除电路耦合到计时计数器和分频器电路，用于检测通电状态，并响应于此，将复位信号施加到分频器和计时计数器电路从而复位 其计数。 检测电路耦合在分配器计时计数器和除法器电路之间，并且适于接收复位信号，并向数字显示器施加第一检查信号，以允许要对数字显示进行第一次检查，直到花时间标准信号 被应用于检查电路。
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12.发明授权System and method for decoding reset signals of a timepiece for providing internal control 失效用于解码用于提供内部控制的时钟的复位信号的系统和方法
公开(公告)号：US3979681A
公开(公告)日：1976-09-07
申请号：US527831
申请日：1974-11-27
申请人： Edward H. Arnold
发明人： Edward H. Arnold
IPC分类号： G01R31/317 , G01R31/3185 , G04D7/12 , H03K21/38 , H03K21/40 , H03K21/32 , G04B19/30 , G04C3/00
CPC分类号： H03K21/38 , G01R31/31701 , G01R31/318527 , G04D7/12 , H03K21/40
摘要： A solid state timepiece having a chain of series connected counters with clock pulses being applied to the first counter in the chain. A reset system is responsive to reset signals and is coupled to the counters for selective resetting of the counters upon application of predetermined reset signals. A decoder system independent of the resetting of the counters detects the state of the reset signals during a predetermined time duration and produces a control signal upon application of selected reset signal states. A control system provides internal control of the timepiece only upon application of the control signal.
摘要翻译： 固态钟表具有串联连接的计数器链，时钟脉冲被施加到链中的第一计数器。 复位系统响应于复位信号，并且耦合到计数器，以在应用预定的复位信号时选择性地重置计数器。 独立于计数器的复位的解码器系统在预定的持续时间内检测复位信号的状态，并在应用所选择的复位信号状态时产生控制信号。 控制系统仅在应用控制信号时提供时钟的内部控制。
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公开(公告)号：US09348317B2
公开(公告)日：2016-05-24
申请号：US13885558
申请日：2011-11-22
摘要： A method of measuring accuracy of a watch including a visual display device, including: storing a first instant, at which the display is in a first display position corresponding to a first image, with a corresponding time reference source; determining a first display value for the first image and stored in a storage in correlation with the first instant; storing, after a determined time interval, a second instant, at which the display is in a second display position corresponding to a second image, with the corresponding source; determining a second display value for the second image and stored in the storage in correlation with the second instant; and calculating displaying on a viewing device the variation in rate of the display.
摘要翻译： 一种测量包括视觉显示装置的手表的精度的方法，包括：将对应于第一图像的显示处于第一显示位置的第一时刻与对应的时间参考源进行存储; 确定第一图像的第一显示值并存储在与第一时刻相关的存储器中; 在确定的时间间隔之后，将对应于第二图像的显示处于第二显示位置的第二时刻与相应的源进行存储; 确定第二图像的第二显示值并与第二时刻相关联地存储在存储器中; 并且在观看设备上计算显示速率的变化。
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14.发明授权
公开(公告)号：US4282595A
公开(公告)日：1981-08-04
申请号：US106173
申请日：1979-12-21
CPC分类号： H03K23/662 , G04D7/12 , G04G13/021
摘要： A method and apparatus for adjusting the frequency of piezoelectric crystal oscillator. The effective frequency of the oscillator is adjusted (trimmed) by periodically inhibiting pulses to the divider stage.The pulse inhibit circuit includes a nonvolatile programmable read-only-memory (ROM) to store binary complement information corresponding to the number of oscillator pulses to be suppressed.A counter is periodically preset with the binary complement information and the count advances in response to oscillator pulses. The difference count between the complement number and the counter's maximum count controls the number of pulses periodically suppressed.During manufacture/assembly of the timepiece, the ROM is programmed to contain the desired complement information.
摘要翻译： 一种用于调节压电晶体振荡器频率的方法和装置。 通过周期性地将脉冲抑制到分频器级来调节（修整）振荡器的有效频率。 脉冲抑制电路包括一个非易失性可编程只读存储器（ROM），用于存储与待抑制的振荡器脉冲数相对应的二进制补码信息。 周期性地用二进制补码信息预设计数器，并且响应于振荡器脉冲计数。 补码和计数器的最大计数之间的差值计数控制周期性抑制的脉冲数。 在制造/组装时钟期间，ROM被编程为包含所需的补码信息。
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15.发明授权
公开(公告)号：US4250574A
公开(公告)日：1981-02-10
申请号：US958435
申请日：1978-11-07
申请人： Claude Mutrux
发明人： Claude Mutrux
摘要： The invention relates to an electronic timepiece in which an input terminal of the integrated circuit is used as an output terminal. During the manufacturing of the timepiece it is important to check the running of the frequency of the oscillator and the operation of at least part of the frequency divider chain. However, in a timepiece, the places available for obtaining measurements could be very limited, and the timepiece does not generally have an output terminal adapted to connect the signal to be measured to an external counter. The purpose of the invention is to utilize an already existing input terminal as an output terminal for permitting a precise and rapid checking of the frequency of the oscillator by measuring, on that terminal, a signal of intermediate frequency delivered by the frequency divider chain. A decoupling circuit permits the terminal to be utilized as an output terminal because it is arranged such that a logic signal delivered to its input is transmitted to its output to the exclusion of the signal of intermediate frequency.
摘要翻译： 本发明涉及一种电子表，其中集成电路的输入端用作输出端。 在制造钟表期间，重要的是检查振荡器频率的运行和至少部分分频器链的运行。 然而，在钟表中，可用于获得测量的位置可能非常有限，并且钟表通常不具有适于将待测量的信号连接到外部计数器的输出端子。 本发明的目的是利用已经存在的输入端子作为输出端子，通过在该端子上测量由分频器链输送的中频信号来允许对振荡器频率的精确和快速检查。 解耦电路允许将端子用作输出端子，因为它被布置为使得传递到其输入的逻辑信号被发送到其输出以排除中频信号。
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公开(公告)号：US4165605A
公开(公告)日：1979-08-28
申请号：US801376
申请日：1977-05-27
申请人： Toshio Kashio
发明人： Toshio Kashio
摘要： An electronic timepiece comprises a reference oscillator, a counter for counting reference clock signals from the reference oscillator to obtain a time count signal, and a display device for displaying a time count value of the counter, in which there is provided an input terminal detachably connected to an external data supply device to permit a preset initial count value data to be inputted from the outside. A master device for the timepiece includes an output terminal detachably connected to the input terminal of the timepiece. The preset initial count value data is supplied to the counter of the timepiece through the output terminal which is detachably connected to the input terminal of the timepiece.
摘要翻译： 电子钟表包括基准振荡器，用于对来自基准振荡器的参考时钟信号进行计数以获得时间计数信号的计数器和用于显示计数器的时间计数值的显示装置，其中提供了一个可拆卸地连接的输入端子 到外部数据供给装置，以允许从外部输入预设的初始计数值数据。 钟表的主装置包括可拆卸地连接到钟表的输入端的输出端。 预设的初始计数值数据通过可拆卸地连接到钟表的输入端子的输出端子提供给计时器的计数器。
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公开(公告)号：US4030338A
公开(公告)日：1977-06-21
申请号：US694574
申请日：1976-06-10
申请人： Heihachiro Ebihara
发明人： Heihachiro Ebihara
摘要： An apparatus for testing the accuracy of a timepiece comprising a television camera for converting the time displayed into an electrical signal, a means for converting the electrical signal into a digital signal, and a processing means for storing the digital signal and comparing the digital signal to a signal corresponding to a time standard. In operation, the time displayed on the timepiece is compared to the time standard at two different times and the difference between the time standard and the time displayed of the two measurements is compared.
摘要翻译： 一种用于测试时钟精度的装置，包括用于将显示的时间转换为电信号的电视摄像机，用于将电信号转换为数字信号的装置，以及用于存储数字信号并将数字信号与 对应于时间标准的信号。 在操作中，将时钟上显示的时间与两个不同时间的时间标准进行比较，并比较两个测量时间标准与显示时间之间的差异。
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18.发明授权
公开(公告)号：US3864957A
公开(公告)日：1975-02-11
申请号：US22472272
申请日：1972-02-09
申请人： SUWA SEIKOSHA KK
发明人： FUJITA KINJI
摘要： For measuring the timing of quartz crystal timepieces there is provided a microphone pickup which is adapted to pick up vibrations from the casing of the timepiece and to convert these mechanical vibrations into an electronic or electrical signal which is amplified and fed to a crystal filter, the filtered signal then being further amplified and supplied to a counter. This enables the vibrations generated within the casing by a quartz crystal to be measured and the accuracy of the timepiece to be checked.
摘要翻译： 为了测量石英晶体钟表的时间，提供了一种麦克风拾音器，其适于从钟表的外壳拾取振动，并将这些机械振动转换成放大并馈送到晶体滤波器的电子或电信号， 滤波后的信号进一步放大并提供给计数器。 这样可以测量由壳体内的石英晶体产生的振动并检查钟表的精度。
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公开(公告)号：US2437929A
公开(公告)日：1948-03-16
申请号：US39863341
申请日：1941-06-18
申请人： HAMILTON WATCH CO
IPC分类号： G04D7/12
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公开(公告)号：US09383725B2
公开(公告)日：2016-07-05
申请号：US14944990
申请日：2015-11-18
摘要： A device for measuring the accuracy of a mechanical watch includes a time reference source, a calculating mechanism, and another data processing unit. The time reference source is formed by an internal time reference source, or by a receiving and processing mechanism arranged to receive and process signals transmitted by an external time source to permanently update a repeater clock internal to the device. The calculating mechanism is arranged to calculate time differences between display values, and/or between time reference points provided by the time reference source, and to calculate a variation in rate. The another data processing unit is arranged to store and process at least one variation in rate calculated by the calculating mechanism, and/or a viewing mechanism arranged to display at least one variation in rate calculated by the calculating mechanism.
摘要翻译： 用于测量机械表的精度的装置包括时间参考源，计算机构和另一个数据处理单元。 时间参考源由内部时间参考源或由布置成接收和处理由外部时间源发送的信号以永久更新设备内部的中继器时钟的接收和处理机制形成。 计算机构被配置为计算显示值之间的时间差和/或时间参考源提供的时间参考点之间的时间差，并计算速率的变化。 另一个数据处理单元被布置成存储和处理由计算机构计算的速率的至少一个变化，和/或被布置为显示由计算机构计算的速率的至少一个变化的观察机构。
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