公开(公告)号：US2838675A

公开(公告)日：1958-06-10

申请号：US50512855

申请日：1955-05-02

申请人： NORTH AMERICAN AVIATION INC

发明人： WANLASS CRAVENS L

IPC分类号： G11B5/09 ,  H03K3/012 ,  H03K3/286 ,  H03K17/66

CPC分类号： H03K17/663 ,  G11B5/09 ,  H03K3/012 ,  H03K3/286

公开(公告)号：US20150077171A1

公开(公告)日：2015-03-19

申请号：US14465100

申请日：2014-08-21

申请人： MING-FENG LIN ,  HEP TECH CO., LTD.

发明人： MING-FENG LIN

IPC分类号： H03K17/66

CPC分类号： H03K17/663 ,  H03K17/60 ,  H03K17/68 ,  H03K2217/0009 ,  H03K2217/0036 ,  H03K2217/0054

摘要： A switch includes a first switching member and a latch circuit. A first terminal of the first switching member is electrically connected to a power source, while a second terminal thereof is electrically connected to a loading. The latch circuit includes a first transistor and a second transistor which are mutually electrically connected. The first transistor is electrically connected to the first terminal, and the second transistor is electrically connected to the control terminal. By inputting a trigger voltage to the second transistor, the second transistor and the first switching member are conducted, which makes the first transistor become conductive. After the first transistor becoming conductive, the first transistor provides electricity to the second transistor to cause latching effect, and to consequently keep the first switching member conductive.

摘要翻译： 开关包括第一开关元件和锁存电路。 第一开关构件的第一端子电连接到电源，而其第二端子与负载电连接。 锁存电路包括彼此电连接的第一晶体管和第二晶体管。 第一晶体管电连接到第一端子，并且第二晶体管电连接到控制端子。 通过向第二晶体管输入触发电压，导通第二晶体管和第一开关元件，这使得第一晶体管导通。 在第一晶体管导通之后，第一晶体管向第二晶体管提供电力以引起锁存效应，并因此保持第一开关元件导电。

公开(公告)号：US07881003B1

公开(公告)日：2011-02-01

申请号：US12228162

申请日：2008-08-08

申请人： Farbod Aram ,  Pantas Sutardja

发明人： Farbod Aram ,  Pantas Sutardja

IPC分类号： G11B5/02 ,  G11B5/09

CPC分类号： G11B5/02 ,  G11B2005/0013 ,  H03K17/04123 ,  H03K17/0414 ,  H03K17/663

摘要： A write driver system includes a logic circuit including first switching devices which receive input write signals and generate control signals. A plurality of predriver circuits includes second switching devices and generates drive signals based on the control signals. A write drive circuit includes third switching devices and generates write drive signals based on the drive signals. The third switching devices have higher threshold voltages than the first and second switching devices.

摘要翻译： 写驱动器系统包括逻辑电路，其包括接收输入写入信号并产生控制信号的第一开关器件。 多个预驱动电路包括第二开关装置，并且基于控制信号产生驱动信号。 写驱动电路包括第三开关装置，并根据驱动信号产生写入驱动信号。 第三开关器件具有比第一和第二开关器件更高的阈值电压。

公开(公告)号：US20030234996A1

公开(公告)日：2003-12-25

申请号：US10179561

申请日：2002-06-25

发明人： Tuan V. Ngo

IPC分类号： G11B005/09 ,  G11B005/02

CPC分类号： G11B5/022 ,  G11B5/012 ,  G11B5/02 ,  G11B2005/001 ,  G11B2005/0013 ,  H03K17/663

摘要： A write driver 100, 200, 300 is implemented to provide near-ground common mode output voltages to produce a more symmetrical head voltage swing (i.e. null0.4V from ground to null5V supply voltages). These features help to reduce the effects of common mode impedance associated with the interconnection to the disk drive head to improve overall performance. Lower jitter at high data rates can be achieved when compared to prior art techniques for implementing current mode write drivers. Further, the matched impedance between the write driver 100 and the interconnection 106 eliminates unwanted reflections. ECL level voltage swings (200-500 mV) have replaced more conventional CMOS level voltage swings (5V) to further reduce overall power dissipation associated with the write driver. The small ECL level switching further maintains constant power dissipation with changes in operating frequency and results in less NTLS effects due to quieter supplies.

摘要翻译： 写入驱动器100,200,300被实现以提供近地共模输出电压以产生更对称的头电压摆幅（即，从接地到±5V电源电压的±0.4V）。 这些功能有助于减少与磁盘驱动器头的互连相关联的共模阻抗的影响，以提高整体性能。 与用于实现当前模式写驱动器的现有技术相比，可以实现高数据速率下的较低抖动。 此外，写入驱动器100和互连106之间的匹配阻抗消除了不必要的反射。 ECL电平电压摆幅（200-500 mV）已经取代了更传统的CMOS电平电压摆幅（5V），以进一步降低与写入驱动器相关的整体功耗。 小型ECL电平切换进一步保持功率损耗随着工作频率的变化而增加，由于更安静的电源，导致更少的NTLS效应。

公开(公告)号：US6121800A

公开(公告)日：2000-09-19

申请号：US152869

申请日：1998-09-14

申请人： John D. Leighton ,  Eric Groen

发明人： John D. Leighton ,  Eric Groen

IPC分类号： G11B5/00 ,  G11B5/02 ,  G11B5/09 ,  H03K17/66 ,  H03B1/00

CPC分类号： G11B5/022 ,  G11B5/02 ,  H03K17/663 ,  G11B2005/0013 ,  G11B5/09

摘要： A write driver for an inductive load includes load terminals for connection to an inductive load, and a driver circuit responsive to first and second control signals to supply a drive current through the load in respective first and second directions. A voltage-mode H-bridge connected to the load terminals is operable to selectively supply a voltage across the load terminals and head. Program means operates the voltage-mode H-bridge for a predetermined time period following initiation of the respective first and second control signal to provide a voltage across the load terminals which quickly raises the write current to a steady state condition. Ringing is suppressed by employing an impedance-matched H-bridge for the driver circuit, the impedance-matched H-bridge having an impedance matched to the impedance of a transmission line connecting the load to the terminals.

摘要翻译： 用于感性负载的写驱动器包括用于连接到感性负载的负载端子，以及响应于第一和第二控制信号的驱动电路，以在相应的第一和第二方向上提供驱动电流通过负载。 连接到负载端子的电压模式H桥可操作以选择性地在负载端子和头部之间提供电压。 编程装置在开始相应的第一和第二控制信号之后的预定时间段内操作电压模式H桥，以在负载端子两端提供电压，从而将写入电流快速地提升到稳定状态。 通过对驱动电路采用阻抗匹配H桥来抑制振铃，阻抗匹配H桥具有与将负载连接到端子的传输线的阻抗匹配的阻抗。

公开(公告)号：US5668676A

公开(公告)日：1997-09-16

申请号：US489191

申请日：1995-06-09

申请人： Johannes O. Voorman ,  Hendrik J. Pothast ,  Ho W. Wong-Lam

发明人： Johannes O. Voorman ,  Hendrik J. Pothast ,  Ho W. Wong-Lam

IPC分类号： G11B5/09 ,  G11B5/02 ,  H03K17/66

CPC分类号： G11B5/022 ,  G11B5/02 ,  H03K17/663

摘要： An apparatus for recording on a magnetic record carrier includes a write amplifier comprising four current mirrors which are turned on two at a time by two switchable floating current sources connected between the input terminals of the current mirrors in order to produce a write current of alternating polarity through a write head. The high impedance at the terminals of the write head enables the common-mode voltage across the write head to be fixed at any desired voltage value by means of a common-mode circuit. The symmetrical structure further enables the parasitic capacitances at the write terminals to be neutralized by means of neutralizing capacitors.

摘要翻译： 用于在磁记录载体上记录的装置包括写入放大器，其包括四个电流镜，每个电流镜由连接在电流镜的输入端之间的两个可切换的浮动电流源一次打开，以产生交替极性的写入电流 通过写头。 在写入头的端子处的高阻抗使得能够通过共模电路将写入头两端的共模电压固定在任何所需的电压值。 对称结构进一步使得写入端子处的寄生电容能够通过中和电容中和。

公开(公告)号：US5132600A

公开(公告)日：1992-07-21

申请号：US704306

申请日：1991-05-22

申请人： Hitoshi Kinoshita

发明人： Hitoshi Kinoshita

IPC分类号： H02P7/288 ,  H02P7/00 ,  H03K17/16 ,  H03K17/66

CPC分类号： H03K17/663 ,  H02P7/04

摘要： A load driving circuit includes a pair of push-pull circuits formed of bipolar transistors. A load is connected between the output terminals of the push-pull circuits and the polarity of a current flowing in the load can be changed to drive the load. The pair of push-pull circuits are controlled by means of an output transistor driving circuit. The output transistor driving circuit includes first and second driving transistors for driving output transistors constituting the push-pull circuits and first and second control transistors for preventing the flow of a through current. The emitter and collector of the first control transistor are respectively connected to the emitter and base of the first driving transistor or the emitter and base of the output transistor arranged on the power source side and constituting one push-pull circuit. The emitter and collector of the second control transistor are respectively connected to the emitter and base of the second driving transistor or the emitter and base of the output transistor arranged on the power source side and constituting another push-pull circuit. The conduction states of the first and second driving transistors are controlled by signals set in an inverted phase. The conduction state of the first and second control transistors are respectively controlled by signals which is in the same phase as the signal for controlling the second and first driving transistors.

摘要翻译： 负载驱动电路包括由双极晶体管形成的一对推挽电路。 负载连接在推挽电路的输出端子之间，并且可以改变在负载中流动的电流的极性以驱动负载。 该对推挽电路通过输出晶体管驱动电路来控制。 输出晶体管驱动电路包括用于驱动构成推挽电路的输出晶体管的第一和第二驱动晶体管，以及用于防止通过电流流动的第一和第二控制晶体管。 第一控制晶体管的发射极和集电极分别连接到布置在电源侧的第一驱动晶体管的发射极和基极或输出晶体管的发射极和基极，并构成一个推挽电路。 第二控制晶体管的发射极和集电极分别连接到第二驱动晶体管的发射极和基极，或者连接在电源侧的输出晶体管的发射极和基极，并构成另一个推挽电路。 第一和第二驱动晶体管的导通状态由在反相中设置的信号控制。 第一和第二控制晶体管的导通状态分别由与用于控制第二和第一驱动晶体管的信号处于相同相位的信号控制。

公开(公告)号：US4602309A

公开(公告)日：1986-07-22

申请号：US732316

申请日：1985-05-09

申请人： Maurice Gaude

发明人： Maurice Gaude

IPC分类号： H01H47/32 ,  H01F7/18 ,  H03K17/66 ,  H01H47/00

CPC分类号： H03K17/663 ,  H01F7/1872

摘要： The control circuit according to the invention consists firstly of two control terminals (S.sub.1, S.sub.2) to which drive pulses of at least two different types can be applied, i.e. a first pulse type (S) designed to obtain one position (S) of the solenoid and which present a first level of amplitude, and a second pulse type (R) designed to obtain a second position (R) of the solenoid and which present a second level of amplitude different from that of the pulses (S) of the first type and with the same polarity and secondly, a discrimination circuit (R.sub.1, R.sub.2, A) for the pulses (R, S) of these two types according to their level of amplitude, this discrimination circuit (R.sub.1, R.sub.2, A) being connected to a switching circuit (CS, CS', CR, CR') controlling supply of the solenoid (B). The invention is also applicable to solenoids comprising one coil as well as to solenoids having two separate coils or with a common intermediate connecting point.

摘要翻译： 根据本发明的控制电路首先由两个可以施加至少两种不同类型的驱动脉冲的控制端子（S1，S2）组成，即设计成获得一个位置（S）的第一脉冲类型（S） 螺线管，并且其呈现第一级的振幅;以及第二脉冲型（R），其设计成获得螺线管的第二位置（R），并且其呈现与第一级的脉冲（S）不同的振幅的第二级别 类型并具有相同的极性，其次，根据它们的电平电平，这两种类型的脉冲（R，S）的鉴别电路（R1，R2，A）连接在一起，该鉴别电路（R1，R2，A）被连接 控制螺线管（B）的供给的开关电路（CS，CS'，CR，CR'）。 本发明还可应用于包括一个线圈的螺线管以及具有两个单独线圈或具有公共中间连接点的螺线管。

公开(公告)号：US4500844A

公开(公告)日：1985-02-19

申请号：US496559

申请日：1983-05-20

申请人： Richard J. Lisco

发明人： Richard J. Lisco

IPC分类号： H03F3/38 ,  H03B28/00 ,  H03F3/217 ,  H03K4/06 ,  H03K5/08 ,  H03K17/66 ,  H04M1/00 ,  H04M3/02 ,  H04M19/02

CPC分类号： H03K4/066 ,  H03B28/00 ,  H03F3/217 ,  H03K17/663 ,  H03K5/086 ,  H04M19/023

摘要： A ringing signal generator is disclosed in which a low-level reference ringing signal, generated by a reference waveform generator (101), is amplified by a delta-modulation power amplifier (106, 108). The low-level reference signal is digitally encoded using delta-modulation techniques to generate a high-level digital signal. The high-level digital signal is filtered (421) to remove the high-frequency components therefrom and to decode the digital signal to form the high-level ringing signal that has the same shape and frequency as the reference signal. The delta-modulation power amplifier generates the ringing signal by comparing (401) the reference ringing signal (E.sub.i) with an analog feedback signal (E.sub.f) reconstructed from the high-level digital signal. The resultant binary error signal (E.sub..epsilon.), representing the polarity of the difference between the reference and the feedback signals, is applied to a logic circuit (405) which samples the error signal at a clock rate substantially higher than the frequency of the ringing signal, and generates two binary control signals (+SW, -SW) based upon the error signal at multiple clock instants. These control signals open and close the switching elements (411, 412, 413, 414) in a bridge switch (410) to generate the high-level digital signal.

摘要翻译： 公开了一种振铃信号发生器，其中由参考波形发生器（101）产生的低电平参考振铃信号由Δ调制功率放大器（106,108）放大。 低电平参考信号使用增量调制技术进行数字编码，以产生高电平数字信号。 高电平数字信号被滤波（421）以从其中去除高频分量，并对数字信号进行解码以形成与参考信号具有相同形状和频率的高电平振铃信号。 Δ调制功率放大器通过将参考振铃信号（Ei）与从高电平数字信号重建的模拟反馈信号（Ef）进行比较（401）来产生振铃信号。 表示参考和反馈信号之差的极性的所得到的二进制误差信号（E epsilon）被施加到逻辑电路（405），该逻辑电路以基本上高于振铃频率的时钟速率对误差信号进行采样 信号，并且基于多个时钟时钟的误差信号产生两个二进制控制信号（+＆upbar＆S， - ＆upbar＆S）。 这些控制信号打开和​​关闭桥式开关（410）中的开关元件（411,412,413,414）以产生高电平数字信号。

公开(公告)号：US3927333A

公开(公告)日：1975-12-16

申请号：US45617674

申请日：1974-03-29

申请人： NIPPON ELECTRIC CO

发明人： FURUHASHI TOKIO

IPC分类号： H03F3/18 ,  H03F3/26 ,  H03K17/66 ,  H03K17/60

CPC分类号： H03K17/663 ,  H03F3/26 ,  H03K17/667

摘要： First and second pairs of complementary NPN and PNP transistors have their base and emitter terminals connected in common, a load being disposed intermediate the emitter terminal junctions. By differentially driving the common transistor base junctions a current will flow bidirectionally through the load; and complementary drivers connected to the collectors of a transistor pair provide a current sinking-current source capability at their common collector junction-as for directly driving a logic circuit.

摘要翻译： 第一对和第二对互补NPN和PNP晶体管的基极和发射极端子共同连接，负载设置在发射极端子结之间。 通过差分驱动公共晶体管基极结，电流将双向流过负载; 并且连接到晶体管对的集电极的互补驱动器在其公共集电极结处提供电流吸收电流源能力，以便直接驱动逻辑电路。