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    DECODING MODULE WITH LOGARITHM CALCULATION FUNCTION
    11.
    发明申请
    DECODING MODULE WITH LOGARITHM CALCULATION FUNCTION 审中-公开

    公开(公告)号：US20170222755A1

    公开(公告)日：2017-08-03

    申请号：US15281669

    申请日：2016-09-30

    申请人： MStar Semiconductor, Inc.

    发明人： Yu Hsien KU

    IPC分类号： H04L1/00

    CPC分类号： H04L1/0045 ,  H03M13/1102 ,  H03M13/112 ,  H03M13/2957 ,  H03M13/615 ,  H03M13/6577 ,  H04L1/005 ,  H04L1/0066 ,  H04L1/0071

    摘要： A decoding module for a communication device includes a first calculation circuit, outputting the larger between a first parameter and a second parameter as a first output parameter; a first arithmetic circuit, calculating a first product of a third parameter and a first slope, and a first difference between a first constant and the first product; a second arithmetic circuit, calculating a second product of the third parameter and a second slope, and a second difference between a second constant and the second product; a second calculation circuit, selecting the largest among a third constant, the first difference and the second difference and generating a second output parameter, wherein the third constant is zero; and an addition circuit, adding the first output parameter and the second output parameter to generate output information, according to which the communication device determines a data bit.

    REDUCED COMPLEXITY NON-BINARY LDPC DECODING ALGORITHM
    14.
    发明申请
    REDUCED COMPLEXITY NON-BINARY LDPC DECODING ALGORITHM 有权
    减少复杂非二进制LDPC解码算法

    公开(公告)号：US20150143194A1

    公开(公告)日：2015-05-21

    申请号：US14607039

    申请日：2015-01-27

    申请人： HGST Netherlands B.V.

    发明人： Majid NEMATI ANARAKI ,  Xinde Hu ,  Richard D. Barndt

    IPC分类号： H03M13/11

    CPC分类号： H03M13/458 ,  H03M13/05 ,  H03M13/1105 ,  H03M13/1111 ,  H03M13/1122 ,  H03M13/1128 ,  H03M13/114 ,  H03M13/1162 ,  H03M13/1171 ,  H03M13/255 ,  H03M13/615 ,  H03M13/6505

    摘要： Decoding logic is provided that is operational upon a data buffer to represent a plurality of variable nodes and a plurality of check nodes. For a respective one of the variable nodes, a vector component is selected from a confidence vector associated with the variable node. Using a respective one of the check nodes, a check node return value is calculated based on one or more other vector components from one or more other vectors and one or more vector indices corresponding to the one or more other vector components. The confidence vector is then updated based on the check node return value and an index for the check node return value, and a current state of a memory cell associated with the respective one of the variable nodes is determined based on a location of a primary one of multiple vector components within the updated confidence vector.

    摘要翻译： 提供了在数据缓冲器上可操作以表示多个可变节点和多个校验节点的解码逻辑。 对于相应的一个变量节点，从与变量节点相关联的置信向量中选择向量分量。 使用校验节点中的相应一个，基于来自一个或多个其他向量的一个或多个其他向量分量和对应于一个或多个其它向量分量的一个或多个向量索引来计算校验节点返回值。 然后基于校验节点返回值和校验节点返回值的索引来更新置信向量，并且基于主要位置的位置确定与相应一个变量节点相关联的存储器单元的当前状态 在更新的置信向量内的多个向量分量。

    ENCODER SIGNAL PROCESSING DEVICE, ENCODER, AND SIGNAL PROCESSING METHOD AND RECORDING MEDIUM
    16.
    发明申请
    ENCODER SIGNAL PROCESSING DEVICE, ENCODER, AND SIGNAL PROCESSING METHOD AND RECORDING MEDIUM 审中-公开

    公开(公告)号：US20180041231A1

    公开(公告)日：2018-02-08

    申请号：US15666975

    申请日：2017-08-02

    申请人： FANUC CORPORATION

    发明人： Youhei KONDOU

    IPC分类号： H03M13/33 ,  H03M13/00

    CPC分类号： H03M13/33 ,  G01D5/00 ,  G01D5/2449 ,  G01D5/24495 ,  H03M13/615

    摘要： An encoder signal processing device detects position data at every predetermined time interval from an original signal which is an analog amount generated in an encoder according to movement of a measurement target. The encoder signal processing device includes: an approximate curve calculation unit that calculates an approximate curve of a detection error included in the original signal on the basis of the detection error of the position data at at least three or more points; an approximate error computation unit that computes an approximate value of the detection error of the position data at an arbitrary time point on the basis of the approximate curve of the detection error; and a position data correction unit that corrects the detection error of the position data at the arbitrary time point on the basis of the approximate value of the detection error of the position data.

    SYSTEMS AND METHODS FOR ERROR CORRECTION IN STRUCTURED LIGHT
    17.
    发明申请
    SYSTEMS AND METHODS FOR ERROR CORRECTION IN STRUCTURED LIGHT 有权
    用于结构光的误差校正的系统和方法

    公开(公告)号：US20160255332A1

    公开(公告)日：2016-09-01

    申请号：US14820419

    申请日：2015-08-06

    申请人： QUALCOMM Incorporated

    发明人： James Wilson Nash ,  Kalin Mitkov Atanassov ,  Sergiu Radu Goma

    IPC分类号： H04N13/02 ,  G06F11/10 ,  H04L1/00

    CPC分类号： H04N13/271 ,  G01B11/25 ,  G06F11/07 ,  G06F11/0703 ,  G06F11/0751 ,  G06F11/0793 ,  G06F11/10 ,  H03M13/39 ,  H03M13/47 ,  H03M13/61 ,  H03M13/615 ,  H04L1/0045 ,  H04N13/128 ,  H04N13/161 ,  H04N13/254 ,  H04N13/296

    摘要： Systems and methods for error correction in structured light are disclosed. In one aspect, a method includes receiving, via a receiver sensor, a structured light image of at least a portion of a composite code mask encoding a plurality of codewords, the image including an invalid codeword. The method further includes detecting the invalid codeword. The method further includes generating a plurality of candidate codewords based on the invalid codeword. The method further includes selecting one of the plurality of candidate codewords to replace the invalid codeword. The method further includes generating a depth map for an image of the scene based on the selected candidate codeword. The method further includes generating a digital representation of a scene based on the depth map. The method further includes outputting the digital representation of the scene to an output device.

    摘要翻译： 公开了用于结构光中纠错的系统和方法。 一方面，一种方法包括经由接收器传感器接收编码多个码字的复合码屏蔽的至少一部分的结构光图像，所述图像包括无效码字。 该方法还包括检测无效码字。 该方法还包括基于无效码字生成多个候选码字。 该方法还包括选择多个候选码字中的一个以替换无效码字。 该方法还包括基于所选择的候选码字生成场景图像的深度图。 该方法还包括基于深度图生成场景的数字表示。 该方法还包括将场景的数字表示输出到输出设备。

    Reduced complexity non-binary LDPC decoding algorithm
    18.
    发明授权
    Reduced complexity non-binary LDPC decoding algorithm 有权
    降低复杂度的非二进制LDPC解码算法

    公开(公告)号：US08954820B2

    公开(公告)日：2015-02-10

    申请号：US13764649

    申请日：2013-02-11

    申请人： STEC, Inc.

    发明人： Majid Nemati Anaraki ,  Xinde Hu ,  Richard D. Barndt

    IPC分类号： H03M13/00 ,  H03M13/05 ,  H03M13/11 ,  H03M13/25

    CPC分类号： H03M13/458 ,  H03M13/05 ,  H03M13/1105 ,  H03M13/1111 ,  H03M13/1122 ,  H03M13/1128 ,  H03M13/114 ,  H03M13/1162 ,  H03M13/1171 ,  H03M13/255 ,  H03M13/615 ,  H03M13/6505

    摘要： A custom decoding algorithm is introduced, in connection with a corresponding decoding structure, to resolve many complexity and large memory requirements of known decoders. A system. A variable node forms a confidence vector of four components, one component for each state of a memory cell, and passes the current primary component (e.g., the largest) to one or more check nodes. The check nodes calculate a temporary component and corresponding index based on all components received from the variable nodes, which they pass back to the respective variable nodes. The variable node updates the confidence vector based on the temporary nodes received from respective check nodes, and determines the correct state for corresponding memory cell based on which component in the confidence vector is currently the primary component.

    摘要翻译： 引入定制解码算法，结合相应的解码结构，以解决已知解码器的许多复杂性和大的存储器要求。 一个系统。 变量节点形成四个分量的置信向量，一个分量用于存储器单元的每个状态，并将当前主要分量（例如，最大的）传递到一个或多个校验节点。 校验节点基于从变量节点接收到的所有组件计算临时组件和相应的索引，它们传回给相应的变量节点。 变量节点基于从相应校验节点接收到的临时节点更新置信向量，并且基于置信度向量中的哪个组件当前是主要组件来确定对应的存储器单元的正确状态。

    REDUCED COMPLEXITY NON-BINARY LDPC DECODING ALGORITHM
    19.
    发明申请
    REDUCED COMPLEXITY NON-BINARY LDPC DECODING ALGORITHM 有权
    减少复杂非二进制LDPC解码算法

    公开(公告)号：US20130212451A1

    公开(公告)日：2013-08-15

    申请号：US13764649

    申请日：2013-02-11

    申请人： STEC, Inc.

    发明人： Majid NEMATI ANARAKI ,  Xinde HU ,  Richard D. BARNDT

    IPC分类号： H03M13/05

    CPC分类号： H03M13/458 ,  H03M13/05 ,  H03M13/1105 ,  H03M13/1111 ,  H03M13/1122 ,  H03M13/1128 ,  H03M13/114 ,  H03M13/1162 ,  H03M13/1171 ,  H03M13/255 ,  H03M13/615 ,  H03M13/6505

    摘要： A custom decoding algorithm is introduced, in connection with a corresponding decoding structure, to resolve many complexity and large memory requirements of known decoders. A system. A variable node forms a confidence vector of four components, one component for each state of a memory cell, and passes the current primary component (e.g., the largest) to one or more check nodes. The check nodes calculate a temporary component and corresponding index based on all components received from the variable nodes, which they pass back to the respective variable nodes. The variable node updates the confidence vector based on the temporary nodes received from respective check nodes, and determines the correct state for corresponding memory cell based on which component in the confidence vector is currently the primary component.

    摘要翻译： 引入定制解码算法，结合相应的解码结构，以解决已知解码器的许多复杂性和大的存储器要求。 一个系统。 变量节点形成四个分量的置信向量，一个分量用于存储器单元的每个状态，并将当前主要分量（例如，最大的）传递到一个或多个校验节点。 校验节点基于从变量节点接收到的所有组件计算临时组件和相应的索引，它们传回给相应的变量节点。 变量节点基于从相应校验节点接收到的临时节点更新置信向量，并且基于置信度向量中的哪个组件当前是主要组件来确定对应的存储器单元的正确状态。

    Method and apparatus for generating parity bits in a forward error correction (FEC) system
    20.
    发明授权
    Method and apparatus for generating parity bits in a forward error correction (FEC) system 有权
    用于在前向纠错（FEC）系统中产生奇偶校验位的方法和装置

    公开(公告)号：US06986097B1

    公开(公告)日：2006-01-10

    申请号：US10371560

    申请日：2003-02-21

    申请人： Howard H. Ireland ,  Jeffery T. Nichols

    发明人： Howard H. Ireland ,  Jeffery T. Nichols

    IPC分类号： G06F11/10

    CPC分类号： H03M13/47 ,  H03M13/152 ,  H03M13/615

    摘要： A method and apparatus for performing parity bit generation. The apparatus of the present invention comprises a parity bit generator that multiplies words comprising message bits by a partial parity multiplication sub-matrix to generate intermediate parity values, and recursively adds (modulo-2) respective intermediate values together so that by the end of the recursive process, a final parity vector exists. This final parity vector can then be added to a message word to create a code word. By recursively using the partial parity multiplication sub-matrix in this way, the number of gates needed to perform parity bit generation is kept relatively small. Consequently the amount of power consumed by the parity bit generator during parity bit generation is relatively small. This is in contrast to typical parity bit generators, which multiply all of the message bits by a full parity multiplication matrix without recursion. The typical non-recursive process, which utilizes the complete parity multiplication matrix, requires a very large number of gates and a large area on an IC to implement the parity bit generator. Also, because of the large number of gates associated with parity bit generators that use the typical approach, those generators consume a large amount of power. The method and apparatus of the present invention are suitable for use with an encoder of a forward error correction (FEC) system.

    摘要翻译： 一种用于执行奇偶校验位产生的方法和装置。 本发明的装置包括奇偶校验位产生器，其将包含消息比特的单词乘以部分奇偶校验乘法子矩阵以产生中间奇偶校验值，并将各个中间值递归（模2）加在一起，使得在 递归过程，存在最终奇偶校验向量。 然后可以将该最终奇偶校验向量添加到消息字以创建代码字。 通过以这种方式递归地使用部分奇偶校验乘法子矩阵，执行奇偶校验位产生所需的门数保持相对较小。 因此，奇偶位产生器在奇偶校验位产生期间消耗的功率量相对较小。 这与典型的奇偶校验位产生器相反，奇偶校验位生成器将所有消息位乘以完全奇偶校验乘法矩阵而不进行递归。 利用完整的奇偶校验乘法矩阵的典型非递归过程需要非常大量的门和IC上的大面积来实现奇偶位产生器。 此外，由于与使用典型方法的奇偶校验位发生器相关联的大量门，这些发生器消耗大量的功率。 本发明的方法和装置适用于前向纠错（FEC）系统的编码器。