Generalized write operations verification method

    公开(公告)号:US10380069B2

    公开(公告)日:2019-08-13

    申请号:US15146685

    申请日:2016-05-04

    摘要: A verification architecture described according to embodiments of the present invention validates changes made to metadata and may comprise one or more subsystems and phases. According to some embodiments, the “mkfs” volume creation utility works in cooperation with the device driver to create a file system volume by means of reservation and initialization space for metadata structures inside the device's partition that is reserved for the specific file system volume. The storage device uses a verified area legend when checking write requests after the file system volume has been created. The verified area legends may be stored in a dedicated partition or inside the master boot record (MBR) or Globally Unique Identifier (GUID) partition table (GPT) or special memory chip (NAND flash, for example). Write requests that overlap with any extent of reserved metadata area must be verified to prevent metadata corruption.

    Optimized data layout for object store system

    公开(公告)号:US10289326B2

    公开(公告)日:2019-05-14

    申请号:US14853741

    申请日:2015-09-14

    IPC分类号: G06F12/00 G06F3/06

    摘要: The present disclosure relates to systems and methods of an optimized data layout in an erasure coded storage system. The system may be realized as a deterministic layout of storage devices in an erasure coded storage system. The system implements a method for writing pieces of a data object across storage devices of a specified write set included an erasure coded storage subsystem. The system further implements a method for reading a subset of pieces of a data object from an active read subset of storage devices in a read set included in the erasure coded storage subsystem and restoring the data object from the subset of pieces. The system may further include operating an inactive read subset of storage devices in a read set in a low power mode.

    Non-volatile memory with adjustable cell bit shape

    公开(公告)号:US10229737B2

    公开(公告)日:2019-03-12

    申请号:US15280110

    申请日:2016-09-29

    摘要: Embodiments of the present disclosure generally relate to non-volatile memory and, in particular, non-volatile memory with adjustable cell bit shapes. In one embodiment, an adjustable memory cell is provided. The memory cell generally includes a gate electrode, at least one recording layer and a channel layer. The channel layer generally is capable of supporting a depletion region and is disposed between the gate electrode and the at least one recording layer. In this embodiment, upon activating the gate, the channel layer may be depleted and current initially flowing through the channel may be steered through the at least one recording layer.

    Methods and systems for improving flash memory flushing

    公开(公告)号:US10209891B2

    公开(公告)日:2019-02-19

    申请号:US14833817

    申请日:2015-08-24

    发明人: Daniel Peter Noé

    摘要: Techniques for improving flash memory flushing are disclosed. In some embodiments, the techniques may be realized as a method for improving flash memory flushing including receiving a request to write to flash memory, writing data associated with the request to the flash memory, identifying a pointer to a region bitmap corresponding to a write region for the write request, marking a bit of the region bitmap corresponding to the request as dirty, and updating the pointer, using a pointer management component, to the region bitmap to contain a dirty block count.

    Redundancy of error correction encoded data in a storage system

    公开(公告)号:US10198313B2

    公开(公告)日:2019-02-05

    申请号:US15068491

    申请日:2016-03-11

    IPC分类号: G06F11/00 G06F11/10 G06F11/07

    摘要: A device that provides for redundancy of error correction encoded data includes at least one processor circuit. The at least one processor circuit is configured to perform error correction encoding on data items to generate corresponding codewords, where at least one of the data items may have a different length than at least one other of the data items and each of the codewords is the same length. The at least one processor circuit is further configured to generate a redundancy data item based at least in part on the codewords. The at least one processor circuit is further configured to write the codewords and the redundancy data item to separate blocks of at least one flash memory circuit.

    Hardware efficient fingerprinting

    公开(公告)号:US10078646B2

    公开(公告)日:2018-09-18

    申请号:US14835622

    申请日:2015-08-25

    IPC分类号: G06F17/30 H03M7/30

    摘要: An approach for fingerprinting large data objects at the wire speed has been disclosed. The techniques include Fresh/Shift pipelining, split Fresh, optimization, online channel sampling, and pipelined selection. The architecture can also be replicated to work in parallel for higher system throughput. Fingerprinting may provide an efficient mechanism for identifying duplication in a data stream, and deduplication based on the identified fingerprints may provide reduced storage costs, reduced network bandwidth consumption, reduced processing time and other benefits. In some embodiments, fingerprinting may be used to ensure or verify data integrity and may facilitate detection of corruption or tampering. An efficient manner of generating fingerprints (either via hardware, software, or a combination) may reduce a computation load and/or time required to generate fingerprints.