公开(公告)号：US06613499B2

公开(公告)日：2003-09-02

申请号：US10177439

申请日：2002-06-20

Applicant: Ching-Yu Chang

Inventor： Ching-Yu Chang

IPC: G03F730

CPC classification number: G03F7/3021

Abstract: A development method in a micro-lithographic process uses a surfactant to overcome the hydrophobic nature on the surface of a photo-resist layer. A developer mixture formed by mixing a developer with a surfactant is used for developing the photo-resist layer. Instead of mixing with the developer, the surfactant may be used to cover the surface of the photo-resist layer before developing. Alternatively, the surfactant can also be applied to the photo-resist layer after it has been developed into a photo-resist pattern.

公开(公告)号：US06579810B2

公开(公告)日：2003-06-17

申请号：US09885038

申请日：2001-06-21

Applicant: Ching-Yu Chang

Inventor： Ching-Yu Chang

IPC: H01L21302

CPC classification number: G03F7/423 ,  H01L21/31133 ,  H01L21/31138

Abstract: A method of removing a photoresist layer on a semiconductor wafer starts with placing the semiconductor wafer into a dry strip chamber. A dry stripping process is performed to remove the photoresist layer on the semiconductor wafer. The semiconductor wafer is then placed on a rotator of a wet clean chamber and horizontally rotated. A first cleaning process is performed to remove polymers and organic components on a surface of the semiconductor wafer. Then a second cleaning process is performed as well to remove polymers and particles on the surface of the semiconductor wafer. By performing a third cleaning process, a first cleaning solution employed in the first cleaning process and a second cleaning solution employed in the second cleaning process are removed from the surface of the semiconductor wafer. Finally, the semiconductor wafer is spun dry at the end of the method.

公开(公告)号：US06562144B2

公开(公告)日：2003-05-13

申请号：US09871664

申请日：2001-06-04

Applicant: Ching-Yu Chang

Inventor： Ching-Yu Chang

IPC: B08B308

CPC classification number: B08B3/10 ,  H01L21/02063 ,  Y10S134/902

Abstract: A method is provided for cleaning a surface of a wafer. First, the wafer is placed in a closed cleaning chamber, and then a cleaning agent is infused into the cleaning chamber to a predetermined height, so that the wafer is completely immersed in the cleaning agent. Next, the pressure in the cleaning chamber is lowered to a sub-atmospheric state of 0.1 to 0.5 atm with a vacuum pump, and then returned to the normal value to complete the cleaning process.

Abstract translation: 提供了一种清洁晶片表面的方法。 首先，将晶片放置在封闭的清洁室中，然后将清洁剂注入清洁室至预定的高度，使得晶片完全浸入清洁剂中。 接下来，用真空泵将清洗室内的压力降至0.1〜0.5atm的亚大气压状态，然后返回正常值，完成清洗处理。

公开(公告)号：US06555468B2

公开(公告)日：2003-04-29

申请号：US09799004

申请日：2001-03-06

Applicant: Ching-Yu Chang

Inventor： Ching-Yu Chang

IPC: H01L214763

CPC classification number: H01L21/76807 ,  H01L21/76224 ,  H01L21/76802

Abstract: A method of fabricating trench is disclosed. A first inter-metal dielectrics (IMD) layer, a mask layer and a second IMD layer are formed sequentially on a semiconductor substrate. Afterwards, a first phototresist layer is formed on the second IMD layer. Thereafter, a photolithography and etching process are performed to transfer a photo mask pattern to form a first opening inside the IMD layer wherein the mask layer serves as an etching stop layer. Subsequently, a second phototresist layer is formed on the second IMD layer and inside the first opening sidewall. A portion of the second phototresist layer on the first IMD layer is removed, and simultaneously the mask layer and the first IMD layer is etched to form a second opening until the semiconductor substrate is exposed. Eventually, the first phototresist layer and the second phototresist layer are stripped simultaneously so as to form a trench having the first opening and the second opening.

Abstract translation: 公开了一种制造沟槽的方法。 在半导体衬底上依次形成第一金属间介电层（IMD）层，掩模层和第二IMD层。 之后，在第二IMD层上形成第一光致抗蚀剂层。 此后，进行光刻和蚀刻处理以转印光掩模图案，以在IMD层内形成第一开口，其中掩模层用作蚀刻停止层。 随后，在第二IMD层上和第一开口侧壁内部形成第二光致抗蚀剂层。 去除第一IMD层上的第二光致抗蚀剂层的一部分，同时蚀刻掩模层和第一IMD层以形成第二开口直到半导体衬底露出。 最终，同时剥离第一光致抗蚀剂层和第二光致抗蚀剂层，以形成具有第一开口和第二开口的沟槽。

公开(公告)号：US06479387B2

公开(公告)日：2002-11-12

申请号：US09682051

申请日：2001-07-15

Applicant: Ching-Yu Chang

Inventor： Ching-Yu Chang

IPC: H01L2144

CPC classification number: H01L21/31053 ,  C09G1/02 ,  C11D1/10 ,  C11D1/123 ,  C11D1/146 ,  C11D1/345 ,  C11D1/62 ,  C11D1/72 ,  C11D11/0047 ,  H01L21/76224

Abstract: The present invention provides a method of reducing micro-particle adsorption effects during a CMP process, to thereby reduce micro-particle adsorption effects on a surface of a semiconductor wafer comprising a silicon nitride layer. The method uses polishing slurry containing anionic surfactant to change the zeta potential of the silicon nitride. Therefore, during the CMP process, the surface of the silicon nitride layer and the micro-particles bare the same type of charges, so as to reduce micro-particle adsorption effects on the surface of the semiconductor wafer.

公开(公告)号：US06458657B1

公开(公告)日：2002-10-01

申请号：US09726460

申请日：2000-11-30

Applicant: Ching-Yu Chang

Inventor： Ching-Yu Chang

IPC: H01L21336

CPC classification number: H01L21/28273 ,  H01L21/76804

Abstract: A method of fabricating a gate. A gate dielectric layer is formed, and a lower portion of a floating gate is formed encompassed by a first dielectric layer. Second dielectric layers with different etching rates are formed to cover the upper portion of the floating gate and the first dielectric layer. Using an etching mask, an opening is formed within the second dielectric layer to expose the floating gate and a portion of the second dielectric layers by performing an anisotropic etching process. Using the same etching mask, the second dielectric layers exposed within the opening is further etched by performing an isotropic etching process. Due to the different etching rates, a dielectric layer with an uneven and enlarged surface is formed. A conformal conductive layer is formed on the exposed lower portion of the floating gate and the exposed second dielectric layers as an upper portion of the floating gate. A conformal third dielectric layer is formed on the conformal conductive layer, followed by forming a control gate on the third dielectric layer.

Abstract translation: 一种制造栅极的方法。 形成栅极电介质层，并且由第一介电层包围浮动栅极的下部。 形成具有不同蚀刻速率的第二电介质层以覆盖浮置栅极和第一介电层的上部。 使用蚀刻掩模，通过执行各向异性蚀刻工艺，在第二介电层内形成开口以暴露浮置栅极和第二介电层的一部分。 使用相同的蚀刻掩模，通过执行各向同性蚀刻工艺进一步蚀刻在开口内暴露的第二电介质层。 由于不同的蚀刻速率，形成具有不均匀和扩大的表面的电介质层。 在浮动栅极的暴露的下部和作为浮动栅极的上部的暴露的第二介电层形成保形导电层。 在保形导电层上形成保形第三电介质层，随后在第三电介质层上形成控制栅极。

公开(公告)号：US06440842B1

公开(公告)日：2002-08-27

申请号：US09851575

申请日：2001-05-10

Applicant: Ching-Yu Chang

Inventor： Ching-Yu Chang

IPC: H01L214763

CPC classification number: H01L21/76885 ,  H01L21/76807 ,  H01L2221/1026

Abstract: A semiconductor wafer comprises a substrate, and a conductive area positioned on a predetermined area of the substrate. A sacrificial layer is formed on the surface of the substrate. A patterned first photoresist layer is formed on the surface of the sacrificial layer, covering the conductive area, followed by removal of the sacrificial layer not covered by the first photoresist layer. A dielectric layer is formed on the surface of the substrate, and a second photoresist layer is formed on the surface of the dielectric layer. A line-shaped opening is formed in the second photoresist layer, followed by etching portions of the dielectric layer through the line-shaped opening for forming a line-shaped recess. The second photoresist layer and the remaining sacrificial layer are completely removed for forming a plug hole in the bottom of the line-shaped recess. Finally, a metal conductive wire and a conductive plug are formed in the line-shaped recess and in the plug hole, with the metal conductive wire coupled with the conductive plug defining a dual damascene structure.

Abstract translation: 半导体晶片包括基板和位于基板的预定区域上的导电区域。 牺牲层形成在基板的表面上。 在牺牲层的表面上形成图案化的第一光致抗蚀剂层，覆盖导电区域，然后除去未被第一光致抗蚀剂层覆盖的牺牲层。 在基板的表面上形成电介质层，在电介质层的表面上形成第二光致抗蚀剂层。 在第二光致抗蚀剂层中形成线状开口，然后通过用于形成线状凹部的线状开口蚀刻介电层的部分。 完全去除第二光致抗蚀剂层和剩余的牺牲层，以在线状凹部的底部形成插塞孔。 最后，金属导电线和导电塞形成在线状凹部和插塞孔中，金属导线与导电插塞连接，限定双镶嵌结构。

公开(公告)号：US06300200B1

公开(公告)日：2001-10-09

申请号：US09750081

申请日：2000-12-29

Applicant: Ching-Yu Chang

Inventor： Ching-Yu Chang

IPC: H01L218246

CPC classification number: H01L27/1126 ,  H01L27/112

Abstract: A method of fabricates a non-volatile ROM device on a semiconductor substrate with a plurality of parallel buried bit lines, a gate oxide layer above the substrate and word lines formed above the gate oxide layer comprises: forming a dielectric layer over the word lines and gate oxide layer, forming and pattern first photoresist layer over the dielectric layer, etching the dielectric layer, stripping the first photoresist layer, forming and pattern second photoresist layer over the dielectric layer to develop an opening area for ion implantation, ion implanting a code implant dopant through the opening area down into the substrate and stripping the second photoresist layer.

Abstract translation: 一种在具有多个并行掩埋位线的半导体衬底上制造非易失性ROM器件的方法，在衬底上方的栅氧化层和形成在栅氧化层上方的字线​​包括：在字线之上形成介电层， 栅极氧化物层，在电介质层上形成和图案化第一光致抗蚀剂层，蚀刻电介质层，剥离第一光致抗蚀剂层，在电介质层上形成和图案化第二光致抗蚀剂层，以形成用于离子注入的开口区域， 掺杂剂通过开口区域向下进入衬底并剥离第二光致抗蚀剂层。

公开(公告)号：US3656808A

公开(公告)日：1972-04-18

申请号：US3656808D

申请日：1970-06-09

Applicant: CHING YU CHANG

Inventor： CHANG CHING-YU

IPC: A47C5/06 ,  A47C1/12

CPC classification number: A47C5/06 ,  Y10S297/11

Abstract: A chair characterized by a frame structure formed by a single frame member having a continuously curved shape. The frame member includes an arcuate planar floor engaging portion, an arcuate inclined riser portion, and an inclined arcuate seat support portion. A seat is suspended from the frame seat support portion and may be fabricated of flexible material such as fabric, or may be of a rigid material such as molded plastic.

Abstract translation: 一种椅子，其特征在于由具有连续弯曲形状的单个框架构件形成的框架结构。 框架构件包括弓形平面地板接合部分，弓形倾斜立管部分和倾斜弓形座椅支撑部分。 座椅从框架座支撑部分悬挂并且可以由诸如织物的柔性材料制成，或者可以是诸如模制塑料的刚性材料。

公开(公告)号：US09256133B2

公开(公告)日：2016-02-09

申请号：US13548557

申请日：2012-07-13

Applicant: Ching-Yu Chang

Inventor： Ching-Yu Chang

IPC: H01L21/47 ,  G03F7/30

CPC classification number: G03F7/3021 ,  G03F7/30

Abstract: An apparatus includes at least two tanks, at least two pumps, at least one nozzle, and a chuck. The apparatus provides multiple developers with different polarities during a developing process to target portions of a latent resist profile having different polarities, and thus different solubility. This apparatus also allows a mixture of two developers to be used for the resist film developing. A polarity of the mixture is adjustable by controlling a ratio of one pump flow rate to another pump flow rate and further controlling the resist pattern profile.

Abstract translation: 一种装置包括至少两个罐，至少两个泵，至少一个喷嘴和卡盘。 该装置在显影过程中提供具有不同极性的多个显影剂，以靶向具有不同极性的潜像抗蚀剂图案的部分，因此具有不同的溶解度。 该装置还允许将两种显影剂的混合物用于抗蚀剂膜显影。 通过控制一个泵流量与另一个泵流量的比率并进一步控制抗蚀剂图形轮廓，可以调节混合物的极性。