公开(公告)号：US06901014B2

公开(公告)日：2005-05-31

申请号：US10445468

申请日：2003-05-27

Applicant: Young-Jae Son ,  Uk-Rae Cho ,  Kwang-Jin Lee

Inventor： Young-Jae Son ,  Uk-Rae Cho ,  Kwang-Jin Lee

IPC: G01R31/28 ,  G11C11/413 ,  G11C29/00 ,  G11C29/06 ,  G11C29/50

CPC classification number: G11C29/12005 ,  G11C11/41 ,  G11C29/50 ,  G11C2029/5002 ,  G11C2029/5006

Abstract: Circuits and methods that enable screening for defective or weak memory cells in a semiconductor memory device. In one aspect, a semiconductor memory device comprises first and second drivers for a SRAM cell. The first driver is connected between a power supply voltage and the cell, which supplies the power supply voltage into the cell in response to a cell power control signal. The second driver is connected between the power supply signal and the cell, which supplies a voltage lower than the power supply voltage into the cell in response to the cell power down signal. A method for screening for defective or weak cells does not require a time for stabilizing a circuit condition after voltage variation to supply the voltage lower than the power supply voltage from a conventional tester because the cell power down signal activates a driver that causes a supply voltage that is lower than the power supply voltage to be loaded directly to the cell, which results in a reduction of the test time for screening defective cells.

Abstract translation: 能够筛选半导体存储器件中的缺陷或弱存储器单元的电路和方法。 在一个方面，半导体存储器件包括用于SRAM单元的第一和第二驱动器。 第一驱动器连接在电源电压和电池之间，其响应于电池功率控制信号将电源电压提供给电池。 第二驱动器连接在电源信号和单元之间，其响应于单元断电信号而向电池提供低于电源电压的电压。 用于筛选有缺陷或弱电池的方法不需要时间来稳定电压变化之后的电路状况，以从常规测试器提供低于电源电压的电压，因为电池停电信号激活导致电源电压的驱动器 低于要直接加载到电池的电源电压，这样可以减少用于筛选有缺陷的电池的测试时间。

公开(公告)号：US06834366B2

公开(公告)日：2004-12-21

申请号：US09957885

申请日：2001-09-21

Applicant: Nam-Seog Kim ,  Kwang-Jin Lee

Inventor： Nam-Seog Kim ,  Kwang-Jin Lee

IPC: G01R3128

CPC classification number: G11C29/12005 ,  G01R31/318572 ,  G11C29/1201 ,  G11C29/48 ,  G11C29/50 ,  G11C2029/3202

Abstract: A circuit and method for selectively outputting internal information in a semiconductor memory device comprising a test circuit such as a JTAG test circuit. The internal information is selectively output through a test pin of the test circuit during a normal operation mode of the semiconductor memory. The internal information of a semiconductor memory chip is output as either a digital or analog signal without having to add additional package pins.

Abstract translation: 一种用于选择性地输出半导体存储器件中的内部信息的电路和方法，包括诸如JTAG测试电路的测试电路。 在半导体存储器的正常操作模式期间，通过测试电路的测试引脚选择性地输出内部信息。 半导体存储器芯片的内部信息作为数字或模拟信号输出，而不必添加额外的封装引脚。

公开(公告)号：US06583647B2

公开(公告)日：2003-06-24

申请号：US10055206

申请日：2002-01-23

Applicant: Nam-Seog Kim ,  Uk-Rae Cho ,  Kwang-Jin Lee

Inventor： Nam-Seog Kim ,  Uk-Rae Cho ,  Kwang-Jin Lee

IPC: H03K190175

CPC classification number: H03K3/356113 ,  H03K3/356165 ,  H03K5/06

Abstract: A level converting apparatus for converting an original voltage level to a wanted voltage level is disclosed. The level converter includes a converting part for outputting a level-converting signal having a different level from that of an input signal in response to an input signal; a delay part for delaying the level-converted signal of the converting part by a predetermined time; and a self-reset part for generating a reset signal in response to the delayed level-converted signal of the delay part to output it to the converting part so that a pulse width of the level-converted signal as output is set as much as the sum of a predetermined delay time and an internal operation delay time.

Abstract translation: 公开了一种用于将原始电压电平转换成所需电压电平的电平转换装置。 电平转换器包括转换部分，用于响应于输入信号输出具有与输入信号不同的电平的电平转换信号; 用于将转换部分的电平转换信号延迟预定时间的延迟部分; 以及自复位部分，用于响应于延迟部分的延迟电平转换信号产生复位信号，以将其输出到转换部分，使得作为输出的电平转换信号的脉冲宽度设置为 预定延迟时间和内部操作延迟时间的和。