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    Signal converting system having level converter for use in high speed semiconductor device and method therefor
    2.
    发明授权
    Signal converting system having level converter for use in high speed semiconductor device and method therefor 有权
    具有用于高速半导体器件的电平转换器的信号转换系统及其方法

    公开(公告)号：US06583647B2

    公开(公告)日：2003-06-24

    申请号：US10055206

    申请日：2002-01-23

    申请人： Nam-Seog Kim ,  Uk-Rae Cho ,  Kwang-Jin Lee

    发明人： Nam-Seog Kim ,  Uk-Rae Cho ,  Kwang-Jin Lee

    IPC分类号： H03K190175

    CPC分类号： H03K3/356113 ,  H03K3/356165 ,  H03K5/06

    摘要： A level converting apparatus for converting an original voltage level to a wanted voltage level is disclosed. The level converter includes a converting part for outputting a level-converting signal having a different level from that of an input signal in response to an input signal; a delay part for delaying the level-converted signal of the converting part by a predetermined time; and a self-reset part for generating a reset signal in response to the delayed level-converted signal of the delay part to output it to the converting part so that a pulse width of the level-converted signal as output is set as much as the sum of a predetermined delay time and an internal operation delay time.

    摘要翻译： 公开了一种用于将原始电压电平转换成所需电压电平的电平转换装置。 电平转换器包括转换部分，用于响应于输入信号输出具有与输入信号不同的电平的电平转换信号; 用于将转换部分的电平转换信号延迟预定时间的延迟部分; 以及自复位部分，用于响应于延迟部分的延迟电平转换信号产生复位信号，以将其输出到转换部分，使得作为输出的电平转换信号的脉冲宽度设置为 预定延迟时间和内部操作延迟时间的和。

    Semiconductor memory device capable of performing high-frequency wafer test operation
    3.
    发明授权
    Semiconductor memory device capable of performing high-frequency wafer test operation 有权
    能够进行高频晶片测试操作的半导体存储器件

    公开(公告)号：US06785173B2

    公开(公告)日：2004-08-31

    申请号：US10352163

    申请日：2003-01-28

    申请人： Kwon-Il Sohn ,  Uk-Rae Cho ,  Kwang-Jin Lee

    发明人： Kwon-Il Sohn ,  Uk-Rae Cho ,  Kwang-Jin Lee

    IPC分类号： G11C2900

    CPC分类号： G11C29/12015 ,  G11C29/14

    摘要： A semiconductor memory device generates a test clock signal (whose periods and cycle number are variable) having a shorter cycle than that of an external clock signal, and internally test data using the test clock signal. The semiconductor memory device may repeatedly perform read/write operations using the internally generated test clock signal during a half cycle of the external clock signal. By comparing output data in the read operation with known data, a test apparatus may determine whether memory cells of a memory device are normal. In a low-frequency test apparatus, it is possible to screen disadvantages that may occur when a high-speed memory device operates at a high frequency.

    摘要翻译： 半导体存储器件产生具有比外部时钟信号更短周期的测试时钟信号（其周期和周期数可变），并且使用测试时钟信号内部测试数据。 半导体存储器件可以在外部时钟信号的半周期期间使用内部产生的测试时钟信号重复执行读/写操作。 通过将读取操作中的输出数据与已知数据进行比较，测试装置可以确定存储器件的存储器单元是否正常。 在低频测试装置中，可以屏蔽当高速存储器件以高频工作时可能发生的缺点。

    Circuits and methods for screening for defective memory cells in semiconductor memory devices
    5.
    发明授权
    Circuits and methods for screening for defective memory cells in semiconductor memory devices 失效
    用于筛选半导体存储器件中的有缺陷的存储单元的电路和方法

    公开(公告)号：US06901014B2

    公开(公告)日：2005-05-31

    申请号：US10445468

    申请日：2003-05-27

    申请人： Young-Jae Son ,  Uk-Rae Cho ,  Kwang-Jin Lee

    发明人： Young-Jae Son ,  Uk-Rae Cho ,  Kwang-Jin Lee

    IPC分类号： G01R31/28 ,  G11C11/413 ,  G11C29/00 ,  G11C29/06 ,  G11C29/50

    CPC分类号： G11C29/12005 ,  G11C11/41 ,  G11C29/50 ,  G11C2029/5002 ,  G11C2029/5006

    摘要： Circuits and methods that enable screening for defective or weak memory cells in a semiconductor memory device. In one aspect, a semiconductor memory device comprises first and second drivers for a SRAM cell. The first driver is connected between a power supply voltage and the cell, which supplies the power supply voltage into the cell in response to a cell power control signal. The second driver is connected between the power supply signal and the cell, which supplies a voltage lower than the power supply voltage into the cell in response to the cell power down signal. A method for screening for defective or weak cells does not require a time for stabilizing a circuit condition after voltage variation to supply the voltage lower than the power supply voltage from a conventional tester because the cell power down signal activates a driver that causes a supply voltage that is lower than the power supply voltage to be loaded directly to the cell, which results in a reduction of the test time for screening defective cells.

    摘要翻译： 能够筛选半导体存储器件中的缺陷或弱存储器单元的电路和方法。 在一个方面，半导体存储器件包括用于SRAM单元的第一和第二驱动器。 第一驱动器连接在电源电压和电池之间，其响应于电池功率控制信号将电源电压提供给电池。 第二驱动器连接在电源信号和单元之间，其响应于单元断电信号而向电池提供低于电源电压的电压。 用于筛选有缺陷或弱电池的方法不需要时间来稳定电压变化之后的电路状况，以从常规测试器提供低于电源电压的电压，因为电池停电信号激活导致电源电压的驱动器 低于要直接加载到电池的电源电压，这样可以减少用于筛选有缺陷的电池的测试时间。

    Synchronous mirror delay circuit with adjustable locking range
    6.
    发明授权
    Synchronous mirror delay circuit with adjustable locking range 失效
    同步镜延时电路具有可调锁定范围

    公开(公告)号：US06933758B2

    公开(公告)日：2005-08-23

    申请号：US10308453

    申请日：2002-12-03

    申请人： Tae-Hyoung Kim ,  Yong-Jin Yoon ,  Nam-Seog Kim ,  Kwang-Jin Lee

    发明人： Tae-Hyoung Kim ,  Yong-Jin Yoon ,  Nam-Seog Kim ,  Kwang-Jin Lee

    IPC分类号： G06F1/12 ,  G06F1/10 ,  H03K5/15 ,  H03L7/00 ,  H03L7/081 ,  H03L7/087

    CPC分类号： H03L7/0814 ,  H03L7/087

    摘要： A synchronous mirror delay circuit comprises a delay monitor circuit for delaying a reference clock signal from a clock buffer circuit. A forward delay array sequentially delays an output clock signal of the delay monitor circuit to generate delay clock signals, and the mirror control circuit detects a delay clock signal synchronized with the reference clock signal among the delay clock signals. A backward delay array delays a clock signal delayed by the mirror control circuit, and a clock driver receives an output clock signal of the backward delay array to generate the internal clock signal. A locking range control circuit controls a delay time of each clock signal transferred to the delay monitor circuit by the amount of a delay time of each signal transferred to the clock driver when none of delay clock signals of the forward delay array is synchronized with the reference clock signal.

    摘要翻译： 同步镜延迟电路包括用于延迟来自时钟缓冲电路的参考时钟信号的延迟监视电路。 正向延迟阵列顺序地延迟延迟监视电路的输出时钟信号以产生延迟时钟信号，并且镜像控制电路在延迟时钟信号中检测与参考时钟信号同步的延迟时钟信号。 后向延迟阵列延迟由镜像控制电路延迟的时钟信号，并且时钟驱动器接收反向延迟阵列的输出时钟信号以产生内部时钟信号。 当前向延迟阵列的延迟时钟信号与参考信号同步时，锁定范围控制电路控制传送到延迟监视器电路的每个时钟信号的延迟时间达到传送到时钟驱动器的每个信号的延迟时间量 时钟信号。

    Method of outputting internal information through test pin of semiconductor memory and output circuit thereof
    7.
    发明授权
    Method of outputting internal information through test pin of semiconductor memory and output circuit thereof 有权
    通过半导体存储器及其输出电路的测试引脚输出内部信息的方法

    公开(公告)号：US06834366B2

    公开(公告)日：2004-12-21

    申请号：US09957885

    申请日：2001-09-21

    申请人： Nam-Seog Kim ,  Kwang-Jin Lee

    发明人： Nam-Seog Kim ,  Kwang-Jin Lee

    IPC分类号： G01R3128

    CPC分类号： G11C29/12005 ,  G01R31/318572 ,  G11C29/1201 ,  G11C29/48 ,  G11C29/50 ,  G11C2029/3202

    摘要： A circuit and method for selectively outputting internal information in a semiconductor memory device comprising a test circuit such as a JTAG test circuit. The internal information is selectively output through a test pin of the test circuit during a normal operation mode of the semiconductor memory. The internal information of a semiconductor memory chip is output as either a digital or analog signal without having to add additional package pins.

    摘要翻译： 一种用于选择性地输出半导体存储器件中的内部信息的电路和方法，包括诸如JTAG测试电路的测试电路。 在半导体存储器的正常操作模式期间，通过测试电路的测试引脚选择性地输出内部信息。 半导体存储器芯片的内部信息作为数字或模拟信号输出，而不必添加额外的封装引脚。

    Memory device using a variable resistive element
    9.
    发明授权
    Memory device using a variable resistive element 有权
    使用可变电阻元件的存储器件

    公开(公告)号：US08248860B2

    公开(公告)日：2012-08-21

    申请号：US12659840

    申请日：2010-03-23

    申请人： Kwang-Jin Lee ,  Chang-Soo Lee ,  Joon-Min Park ,  Hui-Kwon Seo ,  Qi Wang

    发明人： Kwang-Jin Lee ,  Chang-Soo Lee ,  Joon-Min Park ,  Hui-Kwon Seo ,  Qi Wang

    IPC分类号： G11C16/04

    CPC分类号： G11C13/0097 ,  G11C13/0004 ,  G11C13/0069 ,  G11C2013/0088 ,  G11C2211/5646

    摘要： A memory device includes a memory cell array including a plurality of memory blocks, each memory block including a plurality of memory cells, a plurality of word lines coupled to rows of the plurality of memory cells, a plurality of bit lines coupled to columns of the plurality of memory cells, and a control unit controlling an erase operation so that erase data is simultaneously written in the plurality of memory cells corresponding to an erase unit. A first erase mode may include a first erase unit and a first erase data pattern. A second erase mode may include a second erase unit and a second erase pattern. At least one of the first and second erase units and the first and second erase data patterns are different.

    摘要翻译： 存储器件包括存储单元阵列，该存储单元阵列包括多个存储器块，每个存储器块包括多个存储器单元，耦合到多个存储器单元中的行的多个字线，耦合到多个存储器单元的列的多个位线 多个存储单元，以及控制擦除操作的控制单元，使得擦除数据被同时写入与擦除单元对应的多个存储单元中。 第一擦除模式可以包括第一擦除单元和第一擦除数据模式。 第二擦除模式可以包括第二擦除单元和第二擦除模式。 第一和第二擦除单元以及第一和第二擦除数据模式中的至少一个是不同的。

    Non-volatile memory device using variable resistance element with an improved write performance
    10.
    发明授权
    Non-volatile memory device using variable resistance element with an improved write performance 有权
    使用可变电阻元件的非易失性存储器件具有改进的写入性能

    公开(公告)号：US08194447B2

    公开(公告)日：2012-06-05

    申请号：US12314513

    申请日：2008-12-11

    申请人： Hye-Jin Kim ,  Kwang-Jin Lee ,  Du-Eung Kim ,  Hung-Jun An

    发明人： Hye-Jin Kim ,  Kwang-Jin Lee ,  Du-Eung Kim ,  Hung-Jun An

    IPC分类号： G11C16/04

    CPC分类号： G11C7/1078 ,  G11C5/14 ,  G11C7/1096 ,  G11C13/00 ,  G11C13/0004 ,  G11C13/0038 ,  G11C13/0069 ,  G11C2013/009 ,  G11C2213/72

    摘要： A non-volatile memory device using a variable resistive element includes a memory cell array having a plurality of non-volatile memory cells, a first voltage generator generating a first voltage, a voltage pad receiving an external voltage that has a level higher than the first voltage, a sense amplifier supplied with the first voltage and reading data from the non-volatile memory cells selected from the memory cell array, and a write driver supplied with the external voltage and writing data to the non-volatile memory cells selected from the memory cell array.

    摘要翻译： 使用可变电阻元件的非易失性存储器件包括具有多个非易失性存储器单元的存储单元阵列，产生第一电压的第一电压发生器，接收高于第一电压的电平的外部电压的电压焊盘 电压，提供有第一电压的读出放大器和从存储单元阵列中选择的非易失性存储器单元读取数据，以及提供有外部电压的写入驱动器，并将数据写入从存储器中选择的非易失性存储器单元 单元格阵列。