SEMICONDUCTOR PACKAGE AND METHOD FOR FABRICATING THE SAME

    公开(公告)号:US20250079393A1

    公开(公告)日:2025-03-06

    申请号:US18748354

    申请日:2024-06-20

    Abstract: A semiconductor package includes: a first semiconductor chip including a first substrate and a first through electrode passing through the first substrate, wherein the first substrate has a first active surface and a first non-active surface; a chip structure including a plurality of second semiconductor chips stacked on the first semiconductor chip, wherein each second semiconductor chip includes a second substrate and a second through electrode passing through the second substrate; and a third semiconductor chip disposed on the chip structure, and including a third substrate, wherein the first substrate has a first width and a first thickness, wherein the second substrate has a second width and a second thickness, and the third substrate has a third width and a third thickness, wherein the third thickness is thicker than the second thickness, and the third width is greater than the second width.

    SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING SEMICONDUCTOR PACKAGE

    公开(公告)号:US20250079382A1

    公开(公告)日:2025-03-06

    申请号:US18807488

    申请日:2024-08-16

    Abstract: Provided is a semiconductor package including a lower package substrate including lower insulating layers, a first semiconductor device mounted on the lower package substrate, a core layer on the lower package substrate to be laterally spaced apart from the first semiconductor device, an encapsulation material surrounding the first semiconductor device and covering an upper portion of the core layer, an upper package substrate disposed on the encapsulation material, the upper package substrate including a first upper redistribution layer and a second upper redistribution layer; wherein a first line width and a first line spacing of a first fine pattern of the first upper redistribution pattern are greater than or equal to a corresponding second line width and a corresponding second line spacing of a second fine pattern of the second upper redistribution pattern, respectively.

    INTEGRATED CIRCUIT INCLUDING POWER GATING SWITCH

    公开(公告)号:US20250079310A1

    公开(公告)日:2025-03-06

    申请号:US18806236

    申请日:2024-08-15

    Abstract: An integrated circuit includes: a backside wiring layer on a back side of a substrate, the backside wiring layer including a first backside pattern and a second backside pattern isolated from each other; and a power gating switch on a front side of the substrate, the power gating switch connected to the first and second backside patterns. The power gating switch includes: a first source/drain region connected to the first backside pattern, and configured to receive a first supply voltage from the first backside pattern; a gate line structure configured to receive a power gating signal; and a second source/drain region connected to the second backside pattern, and configured to receive a power signal from the first source/drain region based on the power gating signal.

    SYSTEM AND METHOD FOR EARLY PREFETCH FOR MEMORY DEVICE

    公开(公告)号:US20250077436A1

    公开(公告)日:2025-03-06

    申请号:US18748359

    申请日:2024-06-20

    Abstract: A method and apparatus are provided for performing early prefetch in a memory system. A method includes receiving a data request including an address of a data page stored in a memory device; storing the data request at a first position in a request queue; accessing the data request stored at the first position and performing a first lookup operation for the data request; updating the device request queue, which includes moving the data request stored at the first position to a second position in the request queue; and accessing the data request stored at the second position and performing a second lookup operation for the data request.

    MEMORY DEVICE ERROR CORRECTION
    199.
    发明申请

    公开(公告)号:US20250077349A1

    公开(公告)日:2025-03-06

    申请号:US18430287

    申请日:2024-02-01

    Inventor: Hoyoun Kim

    Abstract: A memory device includes a first memory device configured to store a first error correction code of a first size during a first write operation, a second memory device configured to store a second error correction code of a second size, larger than the first size, during a second write operation, and a control logic circuit configured to control the first memory device and the second memory device. The control logic circuit includes an error correction circuit configured to generate one of the first error correction code and the second error correction code for write data according to puncturing option information.

    STORAGE DEVICE AND HOST DEVICE
    200.
    发明申请

    公开(公告)号:US20250077082A1

    公开(公告)日:2025-03-06

    申请号:US18605333

    申请日:2024-03-14

    Abstract: A storage device comprises a first non-volatile memory, a storage controller configured to receive a memory command for writing data in the first non-volatile memory or reading the data from the first non-volatile memory from a processor of a host device through a first channel, a microcontroller configured to receive a command related to a firmware update executed in the storage device from a baseboard management controller (BMC) of the host device through a second channel different from the first channel, and a second non-volatile memory configured to receive and store firmware data from the BMC of the host device.

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