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    SEMICONDUCTOR PACKAGE
    1.
    发明公开
    SEMICONDUCTOR PACKAGE 审中-公开

    公开(公告)号：US20230253343A1

    公开(公告)日：2023-08-10

    申请号：US18301606

    申请日：2023-04-17

    申请人： Samsung Electronics Co., Ltd.

    发明人： Jin-woo PARK ,  Un-Byoung KANG ,  Jong Ho LEE

    IPC分类号： H01L23/00 ,  H01L23/498 ,  H01L23/14

    CPC分类号： H01L23/562 ,  H01L23/49816 ,  H01L24/14 ,  H01L23/14

    摘要： A semiconductor package includes a first substrate including a circuit pattern and a dummy pattern on an upper face of the first substrate, a solder ball, a second substrate on the first substrate, and an underfill material layer between the first and second substrates. The underfill material layer wraps around the solder ball. The dummy pattern is not electrically connected to the circuit pattern. The first substrate includes a solder resist layer on the circuit pattern and the dummy pattern. The solder resist layer includes a first opening for exposing at least a part of the circuit pattern. The solder ball is in the first opening and electrically insulated from the dummy pattern by the solder resist layer. The second substrate is electrically connected to the first substrate by the solder ball. The second substrate is electrically insulated from the dummy pattern by the solder resist layer.

    SEMICONDUCTOR PACKAGES
    2.
    发明申请
    SEMICONDUCTOR PACKAGES 有权

    公开(公告)号：US20220130802A1

    公开(公告)日：2022-04-28

    申请号：US17571796

    申请日：2022-01-10

    申请人： Samsung Electronics Co., Ltd.

    发明人： Joonho JUN ,  Un-Byoung KANG ,  Sunkyoung SEO ,  Jongho LEE ,  Young Kun JEE

    IPC分类号： H01L25/065 ,  H01L23/00

    摘要： A semiconductor package may include first and second substrates, which are vertically stacked, a semiconductor device layer on a bottom surface of the second substrate to face a top surface of the first substrate, upper chip pads and an upper dummy pad on the top surface of the first substrate, penetration electrodes, which each penetrate the first substrate and are connected to separate, respective upper chip pads, lower chip pads on a bottom surface of the semiconductor device layer and electrically connected to separate, respective upper chip pads, and a lower dummy pad on the bottom surface of the semiconductor device layer and electrically isolated from the upper dummy pad. A distance between the upper and lower dummy pads in a horizontal direction that is parallel to the first substrate may be smaller than a diameter of the lower dummy pad.

    SEMICONDUCTOR PACKAGE
    6.
    发明公开
    SEMICONDUCTOR PACKAGE 审中-公开

    公开(公告)号：US20230420374A1

    公开(公告)日：2023-12-28

    申请号：US18303380

    申请日：2023-04-19

    申请人： SAMSUNG ELECTRONICS CO., LTD.

    发明人： Kwang-Chul CHOI ,  Sang Hyun LEE ,  Un-Byoung KANG ,  Jung Hoon KANG

    IPC分类号： H01L23/538 ,  H01L25/16 ,  H01L23/498

    CPC分类号： H01L23/5383 ,  H01L25/16 ,  H01L23/49816 ,  H01L25/105

    摘要： A semiconductor package includes a package substrate having a first side and an opposite second side, a semiconductor chip on the first side of the package substrate, a capacitor on the second side of the package substrate, a plurality of connecting terminals on the second side of the package substrate, and a metal line within a trench in the package substrate. The trench extends in a first direction, and the metal line is between the capacitor and the plurality of connecting terminals. The metal line is spaced apart from the capacitor in a second direction that is transverse to the first direction, and a distance between the metal line and the capacitor is 100 μm or more and 1000 μm or less.

    SEMICONDUCTOR PACKAGE
    7.
    发明申请
    SEMICONDUCTOR PACKAGE 有权

    公开(公告)号：US20220037261A1

    公开(公告)日：2022-02-03

    申请号：US17349174

    申请日：2021-06-16

    申请人： Samsung Electronics Co., Ltd.

    发明人： Ju-Il CHOI ,  Gyuho KANG ,  Un-Byoung KANG ,  Byeongchan KIM ,  Junyoung PARK ,  Jongho LEE ,  Hyunsu HWANG

    IPC分类号： H01L23/538 ,  H01L23/498 ,  H01L23/00 ,  H01L23/31 ,  H01L25/10

    摘要： A semiconductor package including a redistribution substrate including an insulating layer and redistribution patterns in the insulating layer may be provided. Each of the redistribution patterns may include a via portion, a pad portion vertically overlapping the via portion, and a line portion extending from the pad portion. The via portion, the pad portion, and the line portion may be connected to each other to form a single object. A level of a bottom surface of the pad portion may be lower than a level of a bottom surface of the line portion. A width of the line portion may have a largest value at a level between a top surface of the line portion and the bottom surface of the line portion.

    SEMICONDUCTOR PACKAGE
    8.
    发明申请
    SEMICONDUCTOR PACKAGE 有权

    公开(公告)号：US20210384143A1

    公开(公告)日：2021-12-09

    申请号：US17168337

    申请日：2021-02-05

    申请人： Samsung Electronics Co., Ltd.

    发明人： Jin-woo PARK ,  Un-Byoung KANG ,  Jong Ho LEE

    IPC分类号： H01L23/00 ,  H01L23/14 ,  H01L23/498

    摘要： A semiconductor package includes a first substrate including a circuit pattern and a dummy pattern on an upper face of the first substrate, a solder ball, a second substrate on the first substrate, and an underfill material layer between the first and second substrates. The underfill material layer wraps around the solder ball. The dummy pattern is not electrically connected to the circuit pattern. The first substrate includes a solder resist layer on the circuit pattern and the dummy pattern. The solder resist layer includes a first opening for exposing at least a part of the circuit pattern. The solder ball is in the first opening and electrically insulated from the dummy pattern by the solder resist layer. The second substrate is electrically connected to the first substrate by the solder ball. The second substrate is electrically insulated from the dummy pattern by the solder resist layer.