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    SEMICONDUCTOR PACKAGE
    1.
    发明申请
    SEMICONDUCTOR PACKAGE 有权

    公开(公告)号：US20220165698A1

    公开(公告)日：2022-05-26

    申请号：US17401664

    申请日：2021-08-13

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Dahee Kim ,  Jeongrim Seo ,  Gookmi Song

    IPC: H01L23/00 ,  H01L25/10 ,  H01L23/31 ,  H01L23/538 ,  H01L21/48

    Abstract: A semiconductor package includes: a redistribution substrate including a connection via and a redistribution layer electrically connected to each other, and a redistribution pad electrically connected to the redistribution layer by the connection via, a space pattern separating at least some of the redistribution pads from each other, a dummy metal pattern at least partially surrounded by the space pattern, and a degassing opening passing through at least one of the redistribution pad and the dummy metal pattern; a connection bump electrically connected to the redistribution pad; and a semiconductor chip on the redistribution substrate and including a connection pad electrically connected to the redistribution layer, the redistribution pad including a plurality of protrusions protruding from the same plane in directions different from each other and having a corner having a rounded shape, and the dummy metal pattern includes branch patterns each extending in directions different from one another.

    FAN-OUT LEVEL SEMICONDUCTOR PACKAGE
    2.
    发明申请
    FAN-OUT LEVEL SEMICONDUCTOR PACKAGE 有权

    公开(公告)号：US20250105159A1

    公开(公告)日：2025-03-27

    申请号：US18823171

    申请日：2024-09-03

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Pyunghwa Han ,  Dahee Kim ,  Bongsoo Kim ,  Chobi Kim

    IPC: H01L23/538 ,  H01L23/00 ,  H01L23/16 ,  H01L23/31 ,  H01L23/498 ,  H01L25/10

    Abstract: A semiconductor package includes a first wiring structure, an extension structure disposed on the first wiring structure, including an extension base layer and a plurality of via structures, and having a mounting space passing through the extension base layer. The plurality of via structures include a plurality of via connection patterns, a semiconductor chip disposed in the mounting space and electrically connected to the first wiring structure, a filling insulating layer filling the mounting space, and a second wiring structure disposed on the extension structure and the filling insulating layer and electrically connected to the first wiring structure. Lowermost via connection patterns, among the plurality of via connection patterns, include a plurality of first lower connection pads, and the extension base layer includes base dams respectively passing through the plurality of first lower connection pads.

    STACKED STRUCTURE INCLUDING CONDUCTIVE PATTERN FOR SELF-ALIGNMENT
    3.
    发明申请
    STACKED STRUCTURE INCLUDING CONDUCTIVE PATTERN FOR SELF-ALIGNMENT 有权

    公开(公告)号：US20240404936A1

    公开(公告)日：2024-12-05

    申请号：US18417921

    申请日：2024-01-19

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Gyujin Choi ,  Dahee Kim ,  Jae-Ean Lee ,  Taehoon Lee

    IPC: H01L23/498 ,  H01L23/00 ,  H01L23/48 ,  H01L23/528 ,  H01L25/065

    Abstract: A stacked structure includes a lower substrate and a first semiconductor chip stacked on an upper surface of the lower substrate, the lower substrate includes a lower conductor pattern disposed on the upper surface of the lower substrate, the first semiconductor chip may have first and second surfaces facing each other, the second surface of the first semiconductor chip may face the upper surface of the lower substrate, and the first semiconductor chip may include a first conductor pattern disposed on the second surface. The first conductor pattern may be aligned with the lower conductor pattern in a first direction perpendicular to the upper surface of the lower substrate, and the first conductor pattern may be spaced apart from the lower conductor pattern in the first direction.

    SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING SEMICONDUCTOR PACKAGE
    5.
    发明申请
    SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING SEMICONDUCTOR PACKAGE 有权

    公开(公告)号：US20250079382A1

    公开(公告)日：2025-03-06

    申请号：US18807488

    申请日：2024-08-16

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jaeean Lee ,  Dongwon Kang ,  Dahee Kim ,  Changyeon Song ,  Sunguk Lee

    IPC: H01L23/00 ,  H01L23/31 ,  H01L23/538

    Abstract: Provided is a semiconductor package including a lower package substrate including lower insulating layers, a first semiconductor device mounted on the lower package substrate, a core layer on the lower package substrate to be laterally spaced apart from the first semiconductor device, an encapsulation material surrounding the first semiconductor device and covering an upper portion of the core layer, an upper package substrate disposed on the encapsulation material, the upper package substrate including a first upper redistribution layer and a second upper redistribution layer; wherein a first line width and a first line spacing of a first fine pattern of the first upper redistribution pattern are greater than or equal to a corresponding second line width and a corresponding second line spacing of a second fine pattern of the second upper redistribution pattern, respectively.

    SEMICONDUCTOR PACKAGE
    6.
    发明申请
    SEMICONDUCTOR PACKAGE 有权

    公开(公告)号：US20240387486A1

    公开(公告)日：2024-11-21

    申请号：US18584905

    申请日：2024-02-22

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Dahee Kim ,  Hongwon Kim ,  Jae-Ean Lee ,  Taehoon Lee ,  Gyujin Choi

    IPC: H01L25/16 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L23/498

    Abstract: An example semiconductor package includes a substrate, a first semiconductor chip mounted on the substrate, a mold layer on the substrate to cover the first semiconductor chip, and outer terminals positioned below the substrate. The substrate includes a first interconnection layer, a second interconnection layer on the first interconnection layer, a passive device mounted on a bottom surface of the second interconnection layer, and a connection member at a side of the passive device and between the first interconnection layer and the second interconnection layer to connect the first interconnection layer to the second interconnection layer. The outer terminals are coupled to a bottom surface of the first interconnection layer, the passive device includes a first pad on a top surface of the passive device, and an interconnection pattern of the second interconnection layer contacts the first pad.

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