公开(公告)号：US20250125163A1

公开(公告)日：2025-04-17

申请号：US18778009

申请日：2024-07-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyo-Eun LEE ,  Young Chul KWON

IPC: H01L21/67 ,  H01L21/687

Abstract: An apparatus for dicing a wafer includes a stage configured to receive a wafer, and move the wafer in a first direction, and a plurality of laser heads above the stage along the first direction, and as the stage moves the wafer in the first direction, the plurality of laser heads are configured to emit a plurality of laser beams onto the wafer along a plurality of cutting lines, the plurality of cutting lines extending in the first direction and each cutting line spaced apart from other cutting lines in a second direction, the second direction perpendicular to the first direction.

公开(公告)号：US20250124970A1

公开(公告)日：2025-04-17

申请号：US18905764

申请日：2024-10-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Miji Jang ,  Kyuseok Lee

IPC: G11C11/4091 ,  G11C11/4074 ,  G11C11/4094

Abstract: An offset compensated sense amplifier and a memory device including the same are disclosed. A sense amplifier for sensing and amplifying data stored in a memory cell includes a first sense amplifier circuit including first and second PMOS transistors connected to a first sensing driving signal line and a second sense amplifier circuit including first and second NMOS transistors connected to a second sensing driving signal line. The sense amplifier the sense amplifier is configured to perform an offset compensation operation before sensing and amplifying the data stored in the memory cell, the offset compensation operation including a first offset compensation operation based on a threshold voltage difference between the first NMOS transistor and the second NMOS transistor, and a second offset compensation operation based on a threshold voltage difference between the first PMOS transistor and the second PMOS transistor.

公开(公告)号：US20250124969A1

公开(公告)日：2025-04-17

申请号：US18669633

申请日：2024-05-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Changyoung Lee ,  Yeongwoo Kang ,  Yongjun Kim

IPC: G11C11/4091 ,  G11C11/408

Abstract: Memory devices and methods of operating thereof. A memory device may include a plurality of memory cells each including a cell transistor having a back gate that is shared with a cell transistor of an adjacent memory cell through a back gate line, a forward gate that is connected to a corresponding word line, and a cell capacitor that is connected to a first electrode of the cell transistor; a sub-word line driver configured to apply a word line driving voltage to a selected word line; a back gate driver configured to change a back gate voltage applied to the back gate line from a first voltage level to a second voltage level during an active period in which the selected word line is enabled; and a sense amplifier configured to sense data through bit lines connected to second electrodes of the cell transistors of the plurality of memory cells.

公开(公告)号：US20250124829A1

公开(公告)日：2025-04-17

申请号：US18812633

申请日：2024-08-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Keeeun CHOI ,  Joayoung LEE

IPC: G09G3/00 ,  G06F3/01

Abstract: A method performed by a head mounted display (HMD) device includes: determining a sleep onset preparation start time; and displaying, on a display, a sleep onset preparation screen to which a visual effect is applied, from the sleep onset preparation start time, in a stepwise manner during a sleep onset preparation time interval, where the visual effect that is applied in the stepwise manner comprises a visual effect of switching a virtual screen output through an entire display area of the display to a video see through (VST) screen, where the VST screen displays the virtual screen with a non-virtual screen as a background in the entire display area of the display, where the non-virtual screen is based on an image captured through a front camera, and where the virtual screen is based on content executed by the HMD device.

公开(公告)号：US20250124538A1

公开(公告)日：2025-04-17

申请号：US18999609

申请日：2024-12-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Youngchol LEE ,  Byungseok SOH ,  Bonseuk GOO ,  Youngtae KIM ,  Kisung LEE ,  Weonhee LEE ,  Yongseok JANG

IPC: G06T3/08 ,  G06T7/11 ,  G06T7/50

Abstract: An electronic device includes: a projector; a camera; one or more processors; and memory storing instructions that, when executed by the one or more processors, cause the electronic device to: control the projector to display a projected image on a screen, wherein the screen includes surfaces; control the camera to obtain a captured image including the surfaces and the projected image; identify, based on the captured image, shapes of the surfaces and areas of the projected image projected onto the surfaces; and correct the projected image, based on the shapes of the surfaces and the areas of the projected image, by transforming the projected image into one from among a three-dimensional image and a flat image.

公开(公告)号：US20250124346A1

公开(公告)日：2025-04-17

申请号：US18795490

申请日：2024-08-06

Applicant: Samsung Electronics Co., Ltd. ,  POSTECH RESEARCH AND BUSINESS DEVELOPMENT FOUNDATION

Inventor： Myeongjae LEE ,  Joonhee KIM ,  Soohee HAN ,  Jungsoo KIM ,  Jinho KIM ,  Hangyeol KIM ,  Hyosik MOON ,  Huiyong CHUN

IPC: G06N20/00 ,  G01R31/367 ,  G01R31/389 ,  G01R31/392

Abstract: A method and apparatus for training a short circuit detection model are disclosed. The method includes generating virtual battery models with different battery parameter sets, based on battery data measured by a real battery in a non-short circuit state, by applying a constraint corresponding to a short circuit state to the virtual battery models, generating a virtual test result of the short circuit state, and training a short circuit detection model configured to detect the short circuit state using the virtual test result.

公开(公告)号：US20250123983A1

公开(公告)日：2025-04-17

申请号：US18791405

申请日：2024-07-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongmin GIM ,  Heekwon PARK ,  Jaemin JUNG ,  Changho CHOI ,  Yang Seok KI

IPC: G06F13/40 ,  G06F13/42

Abstract: An apparatus including a switch may include a first interface configured to communicate with at least one memory device, and a second interface configured to communicate with a first physical connector and a second physical connector, where the switch is configured to communicate with a device using the first physical connector using a memory access protocol. The second interface may be configured to communicate with a second device using the second physical connector using the memory access protocol. The apparatus may further include a second switch including a third interface configured to communicate with the at least one memory device, and a fourth interface configured to communicate with a third physical connector and a fourth physical connector, where the second switch may be configured to communicate with the device using the third physical connector using the memory access protocol.

公开(公告)号：US20250123971A1

公开(公告)日：2025-04-17

申请号：US18755026

申请日：2024-06-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jungsik CHOI ,  Ruth KIM ,  Seok-Young YOON

IPC: G06F12/1036 ,  G06F12/0873

Abstract: A processor-implemented method includes receiving a mapping instruction to map target data onto a process address space, in response to reception of the mapping instruction, marking an unused node in a tree that manages the process address space as a use node to reuse, and mapping the target data onto a virtual area in the process address space, wherein the tree manages the virtual area onto which the target data is mapped as the use node.

公开(公告)号：US20250123943A1

公开(公告)日：2025-04-17

申请号：US18909171

申请日：2024-10-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Changyong Oh ,  Byeonghui Kim ,  Seongho Roh ,  Hyeongyu Min ,  Hyunkyo Oh ,  Dongchan Lee ,  Hankyoo Lee ,  Kibeen Jung

IPC: G06F11/34

Abstract: Provided are a method and apparatus for optimizing prefetch performance of a storage device. The method of optimizing prefetch performance of a storage device includes receiving prefetch data from the storage device configured to process a workload based on a parameter, generating prefetch performance data for a plurality of combinations of block size and queue depth, based on the prefetch data, generating index data for evaluating the prefetch performance data, based on the prefetch performance data, updating the parameter to generate an updated parameter based on the index data, and transferring, to the storage device, the updated parameter, wherein the generating of the index data includes generating the index data by taking into account an inversion interval in which prefetch performance decreases with an increase in the block size or the queue depth.

公开(公告)号：US20250123755A1

公开(公告)日：2025-04-17

申请号：US18670908

申请日：2024-05-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Daehyun KIM ,  Suhyun KIM ,  Ikkyun PARK ,  Hyunju YI

IPC: G06F3/06

Abstract: An embodiment of the method includes transferring a first read command corresponding to a first cell region of the memory device through a first channel, receiving first data, read from the first cell region, from the memory device through a second channel physically separated from the first channel, transferring a status information request command through the first channel, the status information request command request the transfer of status information about a second cell region of the memory device, receiving the status information about the second cell region from the memory device through the first channel, and transferring a second read command corresponding to the second cell region of the memory device through the first channel, at least a portion of a period in which the status information is received through the first channel overlaps a period where the first data is received through the second channel.