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公开(公告)号：US20200243604A1
公开(公告)日：2020-07-30
申请号：US16848200
申请日：2020-04-14
Applicant: Micron Technology, Inc.
Inventor： Andrea Redaelli
IPC: H01L27/24 , G11C13/00 , H01L45/00 , G11C11/408 , H01L27/108 , G11C5/02
Abstract: Memory devices for embedded applications are described. A memory device may include an array of memory cells having a first area and configured to operate at a first voltage, and circuitry having a second area that at least partially overlaps the first area. The circuitry may be configured to operate at a second voltage lower than the first voltage. The circuitry maybe be further configured to access the array of memory cells using decoder circuitry configured to operate at the first voltage. The array of memory cells and the circuitry may be on a single substrate. The circuitry may include microcontroller circuitry, cryptographic controller circuitry, and/or memory controller circuitry. The memory cells may be self-selecting memory cells that each include a storage and selector element having a chalcogenide material. The memory cells may not include separate cell selector circuitry.
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公开(公告)号：US20200234747A1
公开(公告)日：2020-07-23
申请号：US16253485
申请日：2019-01-22
Applicant: Micron Technology, Inc.
Inventor： Andrea Redaelli
Abstract: Methods, systems, and devices for a decoder are described. The memory device may include a substrate, an array of memory cells coupled with the substrate, and a decoder coupled with the substrate. The decoder may include a doped material that may extend between a first conductive line and an access line of the array of memory cells in a first direction (e.g., away from a surface of the substrate) and the doped material may be configured to selectively couple the first conductive line of the decoder with the access line of the array of memory cells. The access line may be coupled with two decoders, in some cases.
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公开(公告)号：US10707271B2
公开(公告)日：2020-07-07
申请号：US16216100
申请日：2018-12-11
Applicant: Micron Technology, Inc.
Inventor： Fabio Pellizzer , Andrea Redaelli , Agostino Pirovano , Innocenzo Tortorelli
Abstract: The present disclosure includes memory cells having resistors, and methods of forming the same. An example method includes forming a first conductive line, forming a second conductive line, and forming a memory element between the first conductive line and the second conductive line. Forming the memory element can include forming one or more memory materials, and forming a resistor in series with the one or more memory materials. The resistor can be configured to reduce a capacitive discharge through the memory element during a state transition of the memory element.
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公开(公告)号：US20200176039A1
公开(公告)日：2020-06-04
申请号：US16731948
申请日：2019-12-31
Applicant: Micron Technology, Inc.
Inventor： Andrea Redaelli , Fabio Pellizzer
Abstract: Methods, systems, and devices for a decoder are described. The memory device may include a substrate, an array of memory cells coupled with the substrate, and a decoder coupled with the substrate. The decoder may be configured to apply a voltage to an access line of the array of memory cells as part of an access operation. The decoder may include a first conductive line configured to carry the voltage applied to the access line of the array of memory cells. In some cases, the decoder may include a doped material extending between the first conductive line and the access line of the array of memory cells in a first direction (e.g., away from a surface of the substrate) and the doped material may be configured to selectively couple the first conductive line of the decoder with the access line of the array of memory cells.
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公开(公告)号：US10658428B2
公开(公告)日：2020-05-19
申请号：US16185729
申请日：2018-11-09
Applicant: Micron Technology, Inc.
Inventor： Ugo Russo , Andrea Redaelli , Giorgio Servalli
Abstract: Phase change memory apparatuses include memory cells including phase change material, bit lines electrically coupled to aligned groups of at least some of the memory cells, and heating elements electrically coupled to the phase change material of the memory cells. The heating elements include vertical portions extending in a bit line direction. Additional phase change memory apparatuses include dummy columns positioned between memory columns and base contact columns. The dummy columns include phase change memory cells and lack heating elements coupled to the phase change memory cells thereof. Additional phase change memory apparatuses include heating elements operably coupled to phase change memory cells. An interfacial area between the heating elements and the phase change memory cells has a length that is independent of a bit line width. Methods relate to forming such phase change memory apparatuses.
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Patent Agency Ranking
公开(公告)号：US10600481B2
公开(公告)日：2020-03-24
申请号：US16105874
申请日：2018-08-20
Applicant: Micron Technology, Inc.
Inventor： Agostino Pirovano , Innocenzo Tortorelli , Andrea Redaelli , Fabio Pellizzer
Abstract: Disclosed herein is a memory cell including a memory element and a selector device. The memory cell may be programmed with a programming pulse having a first polarity and read with a read pulse having a second polarity. The memory cell may be programmed with a programming pulse having first and second portions. The first and second portions may have different magnitudes and polarities. The memory cell may exhibit reduced voltage drift and/or threshold voltage distribution. Described herein is a memory cell that acts as both a memory element and a selector device. The memory cell may be programmed with a programming pulse having first and second portions. The first and second portions may have different magnitudes and polarities.
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公开(公告)号：US10553792B2
公开(公告)日：2020-02-04
申请号：US15841356
申请日：2017-12-14
Applicant: Micron Technology, Inc.
Inventor： Andrea Redaelli , Mattia Boniardi , Enrico Varesi , Raffaella Calarco , Jos E. Boschker
Abstract: The present disclosure includes textured memory cell structures and method of forming the same. In one or more embodiments, a memory cell includes a buffer portion formed on an amorphous portion and an active portion formed on the buffer portion, wherein the active portion is textured with a single out of plane orientation.
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公开(公告)号：US10546632B2
公开(公告)日：2020-01-28
申请号：US15842496
申请日：2017-12-14
Applicant: Micron Technology, Inc.
Inventor： Andrea Redaelli , Innocenzo Tortorelli , Agostino Pirovano , Fabio Pellizzer
Abstract: Methods, systems, and devices related to a multi-level self-selecting memory device are described. A self-selecting memory cell may store one or more bits of data represented by different threshold voltages of the self-selecting memory cell. A programming pulse may be varied to establish the different threshold voltages by modifying one or more durations during which a fixed level of voltage or fixed level of current is maintained across the self-selecting memory cell. The self-selecting memory cell may include a chalcogenide alloy. A non-uniform distribution of an element in the chalcogenide alloy may determine a particular threshold voltage of the self-selecting memory cell. The shape of the programming pulse may be configured to modify a distribution of the element in the chalcogenide alloy based on a desired logic state of the self-selecting memory cell.
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公开(公告)号：US20200013463A1
公开(公告)日：2020-01-09
申请号：US16518847
申请日：2019-07-22
Applicant: Micron Technology, Inc.
Inventor： Andrea Redaelli , Agostino Pirovano , Innocenzo Tortorelli , Fabio Pellizzer
Abstract: Methods, systems, and devices for programming enhancement in memory cells are described. An asymmetrically shaped memory cell may enhance ion crowding at or near a particular electrode, which may be leveraged for accurately reading a stored value of the memory cell. Programming the memory cell may cause elements within the cell to separate, resulting in ion migration towards a particular electrode. The migration may depend on the polarity of the cell and may create a high resistivity region and low resistivity region within the cell. The memory cell may be sensed by applying a voltage across the cell. The resulting current may then encounter the high resistivity region and low resistivity region, and the orientation of the regions may be representative of a first or a second logic state of the cell.
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公开(公告)号：US10483463B2
公开(公告)日：2019-11-19
申请号：US16121433
申请日：2018-09-04
Applicant: Micron Technology, Inc.
Inventor： Andrea Redaelli , Giorgio Servalli , Carmela Cupeta , Fabio Pellizzer
Abstract: Some embodiments include methods of forming memory cells. Heater structures are formed over an array of electrical nodes, and phase change material is formed across the heater structures. The phase change material is patterned into a plurality of confined structures, with the confined structures being in one-to-one correspondence with the heater structures and being spaced from one another by one or more insulative materials that entirely laterally surround each of the confined structures. Some embodiments include memory arrays having heater structures over an array of electrical nodes. Confined phase change material structures are over the heater structures and in one-to-one correspondence with the heater structures. The confined phase change material structures are spaced from one another by one or more insulative materials that entirely laterally surround each of the confined phase change material structures.
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