公开(公告)号：US20090316845A1

公开(公告)日：2009-12-24

申请号：US12481375

申请日：2009-06-09

Applicant: Matthew Peter Hutson

Inventor： Matthew Peter Hutson

IPC: H04L7/00

CPC classification number: H04L7/02

Abstract: A system for controlling the transfer of a signal sequence in a first clock domain to a plurality of other clock domains. The system comprising: detecting circuitry for detecting receipt of the signals from the clock domains and setting an update signal when all of the signals received from the clock domains have a common state; and gating circuitry for receiving the update signal and operable, when the update signal is set, to allow a next signal in the sequence to be received at the input of the first circuitry.

Abstract translation: 一种用于控制第一时钟域中的信号序列向多个其它时钟域的传送的系统。 该系统包括：检测电路，用于检测来自时钟域的信号的接收，并且当从时钟域接收的所有信号具有共同的状态时，设置更新信号; 以及用于接收更新信号的选通电路，并且当更新信号被设置时可操作以允许序列中的下一个信号在第一电路的输入处被接收。

公开(公告)号：US07441109B2

公开(公告)日：2008-10-21

申请号：US11384024

申请日：2006-03-17

Applicant: Andrew Cofler ,  Laurent Wojcieszak ,  Isabelle Sename

Inventor： Andrew Cofler ,  Laurent Wojcieszak ,  Isabelle Sename

IPC: G06F7/38

CPC classification number: G06F11/3656 ,  G06F9/3842

Abstract: A computer system with enhanced integrated debug facilities is described. According to one aspect, step-by-step execution of an instruction sequence is implemented where each instruction is guarded. If, after guard resolution, the instruction is committed, a divert routine is executed. If the instruction is not committed, the next instruction in the sequence is executed. According to another aspect, a stall state can be set at the decode unit either by reading stall attributes associated with debug instructions, or responsive to a stall command from an on-chip emulation unit.

Abstract translation: 描述了一种具有增强型集成调试功能的计算机系统。 根据一个方面，执行指令序列的逐步执行，其中每个指令被保护。 如果在保护解决之后，执行指令，则执行转移程序。 如果指令未提交，则执行该顺序中的下一条指令。 根据另一方面，可以通过读取与调试指令相关联的失速属性，或响应来自片上仿真单元的失速命令，在解码单元处设置失速状态。

公开(公告)号：US07437514B2

公开(公告)日：2008-10-14

申请号：US11881400

申请日：2007-07-26

Applicant: Andrew C. Sturges ,  David May

Inventor： Andrew C. Sturges ,  David May

IPC: G06F12/00

CPC classification number: G06F12/0804 ,  G06F12/0842 ,  G06F12/0848 ,  G06F12/0864 ,  G06F12/1045

Abstract: A cache system is provided which includes a cache memory and a cache refill mechanism which allocates one or more of a set of cache partitions in the cache memory to an item in dependence on the address of the item in main memory. This is achieved in one of the described embodiments by including with the address of an item a set of partition selector bits which allow a partition mask to be generated to identify into which cache partition the item may be loaded.

Abstract translation: 提供一种缓存系统，其包括高速缓冲存储器和高速缓冲存储器补充机制，其根据主存储器中的项目的地址将高速缓冲存储器中的一组高速缓存分区中的一个或多个分配给项目。 这在所描述的实施例之一中通过用项目的地址包括一组分区选择器位来实现，所述分组选择器位允许生成分区掩码以识别可以加载该物品的高速缓存分区。

公开(公告)号：US07406113B2

公开(公告)日：2008-07-29

申请号：US10632566

申请日：2003-08-01

Applicant: Philip Mattos ,  Marco Losi

Inventor： Philip Mattos ,  Marco Losi

IPC: H04B1/00

CPC classification number: H04B1/7085 ,  G01S19/29 ,  G01S19/30 ,  H03H17/0664 ,  H04B1/70753 ,  H04B1/709 ,  H04B2201/70715

Abstract: A semiconductor integrated circuit for processing a plurality of received broadcast signals, such as GPS signals, is operable in two modes: acquisition and tracking. In an acquisition mode, sample reducer combines samples of a received signal for correlation with a locally generated version of a GPS code. In a tracking mode, the sampled signal is provided direct to the correlators without sample reduction. The same correlators are thereby used to increase acquisition speed.

Abstract translation: 用于处理诸如GPS信号的多个接收的广播信号的半导体集成电路可以以两种模式进行操作：采集和跟踪。 在采集模式中，采样减速器组合接收信号的样本，以便与本地生成的GPS码版本进行相关。 在跟踪模式中，采样信号直接提供给相关器而不需要样本减少。 因此，使用相同的相关器来提高采集速度。

公开(公告)号：US07403558B2

公开(公告)日：2008-07-22

申请号：US10632530

申请日：2003-08-01

Applicant: Philip Mattos ,  Marco Losi

Inventor： Philip Mattos ,  Marco Losi

IPC: H04B1/00

CPC classification number: G01S19/37 ,  G01S19/24 ,  G01S19/29 ,  G01S19/30 ,  H04B1/708 ,  H04B1/709 ,  H04B2201/70715

Abstract: A semiconductor integrated circuit for processing a plurality of received broadcast signals, such as GPS signals, is operable in two modes: acquisition and tracking. In an acquisition mode, a memory arrangement comprising two circulating shift registers circulates samples of a received signal for correlation with a locally generated version of a GPS code. In a tracking mode, the sampled signal is provided direct to the correlators. The same correlators are thereby used to increase acquisition speed.

Abstract translation: 用于处理诸如GPS信号的多个接收的广播信号的半导体集成电路可以以两种模式进行操作：采集和跟踪。 在采集模式中，包括两个循环移位寄存器的存储装置循环接收信号的采样，以便与本地生成的GPS码版本相关。 在跟踪模式中，采样信号被直接提供给相关器。 因此，使用相同的相关器来提高采集速度。

公开(公告)号：US07366938B2

公开(公告)日：2008-04-29

申请号：US11175108

申请日：2005-07-05

Applicant: Robert Warren ,  David Smith

Inventor： Robert Warren ,  David Smith

IPC: G06F15/177 ,  G06F1/12

CPC classification number: G06F1/24

Abstract: An electronic device having first circuitry operating in a first clock environment and second circuitry operating in a second clock environment, the first circuitry being arranged to generate a soft reset signal for resetting the second circuitry, the integrated circuit further including: a soft reset hold circuit clocked in the first clock environment connected to receive the soft reset signal and to generate an output reset signal in an asserted state; and a synchronizer clocked in the second clock environment connected to receive the output reset signal and to generate a retimed reset signal in an asserted state after a predetermined period, wherein the retimed reset signal is fed back to the soft reset hold circuit to cause the output reset signal to adopt a deasserted state at the end of said predetermined period.

Abstract translation: 一种电子设备，其具有在第一时钟环境中工作的第一电路和在第二时钟环境中工作的第二电路，所述第一电路被布置为产生用于复位所述第二电路的软复位信号，所述集成电路还包括：软复位保持电路 连接在第一时钟环境中的时钟，以接收软复位信号并产生处于断言状态的输出复位信号; 以及在第二时钟环境中被时钟的同步器，连接以接收输出复位信号，并且在预定时间段之后产生处于断言状态的重新定时复位信号，其中重新定时复位信号被反馈到软复位保持电路以使输出 复位信号在所述预定周期结束时采取无效状态。

公开(公告)号：US07356708B2

公开(公告)日：2008-04-08

申请号：US10773089

申请日：2004-02-03

Applicant: Andrew Dellow

Inventor： Andrew Dellow

IPC: H04L9/00 ,  H03K19/00 ,  H04N7/00 ,  G06F15/00

CPC classification number: H04L9/0631 ,  H04L9/0827 ,  H04L2209/601

Abstract: A semiconductor integrated circuit having a plurality of selectable pathways inter-connected to data sources and data destinations; a cryptographic circuit connected to the selectable pathways to selectively receive data from at least one of the data sources, to decrypt or encrypt the data in accordance with a key, and to selectively provide the encrypted or decrypted data to at least one of the data destinations; an instruction interpreter arranged to receive an instruction signal and to generate an output to control the plurality of selectable pathways to select from which of the data sources the cryptographic circuit receives data and to which destination the cryptographic circuit provides data. The instruction interpreter configured such that the instruction signal defines a data pathway that operates in accordance with a rule that limits the data pathway configurations which are selectable.

Abstract translation: 一种具有与数据源和数据目的地相互连接的多个可选路径的半导体集成电路; 连接到所述可选择路径以选择性地从所述数据源中的至少一个数据源接收数据的密码电路，根据密钥对所述数据进行解密或加密，并且选择性地将加密或解密的数据提供给所述数据目的地中的至少一个 ; 指令解释器，被布置为接收指令信号并产生输出以控制多个可选路径，以从密码电路中的哪一个数据源接收数据以及加密电路提供数据的哪个目的地。 指令解释器被配置为使得指令信号定义根据限制可选择的数据路径配置的规则操作的数据通路。

公开(公告)号：US07353508B2

公开(公告)日：2008-04-01

申请号：US10206381

申请日：2002-07-26

Applicant: Antony Bowers ,  Richard Shann

Inventor： Antony Bowers ,  Richard Shann

IPC: G06F9/44

CPC classification number: G06F8/54

Abstract: Call frame information is used by debugging software. It records how to restore the parent stack frame at any point during execution of a program. It is normally generated during compilation and stored in the executable in a compressed format, consisting of sequences of instructions that describe how the current call frame changes during execution of each function. Described herein is a means of generating call frame information at link time, using linker macro calls generated by a small set of assembler macros.

Abstract translation: 呼叫帧信息由调试软件使用。 它记录了在执行程序期间的任何时候如何恢复父堆栈帧。 它通常在编译期间生成并以压缩格式存储在可执行文件中，该格式由描述当前调用帧在每个功能执行期间如何改变的指令序列组成。 这里描述的是使用由一组汇编器宏生成的链接器宏调用在链接时产生呼叫帧信息的手段。

公开(公告)号：US07307631B2

公开(公告)日：2007-12-11

申请号：US10811481

申请日：2004-03-26

Applicant: Mathieu Robart

Inventor： Mathieu Robart

IPC: G06T15/50 ,  G06T15/60 ,  G09G5/00

CPC classification number: G06T15/60

Abstract: An image is rendered which includes at least one light source, a first, shadow-casting object with a second, shadow-receiving object located on the side of the first shadow-casting object remote from said at least one light source. A shadow mask is generated which identifies for each of a plurality of pixels on the shadow receiving surface a grey level representing the intensity of shadow in each pixel. The intensity is determined utilizing the distance between the shadow-casting object and the shadow-receiving object.

Abstract translation: 渲染图像，其包括至少一个光源，第一阴影投射对象，其具有位于远离所述至少一个光源的第一阴影投射对象的一侧上的第二影子接收对象。 产生阴影掩模，其对阴影接收表面上的多个像素中的每一个识别代表每个像素中的阴影强度的灰度级。 使用阴影投射对象和阴影接收对象之间的距离来确定强度。

公开(公告)号：US07253816B2

公开(公告)日：2007-08-07

申请号：US10384183

申请日：2003-03-07

Applicant: Toni Brkic

Inventor： Toni Brkic

IPC: G06T11/20

CPC classification number: G06T11/40

Abstract: A computer graphics accelerator apparatus and method determines whether a pixel at predetermined pixel co-ordinates in an area being rasterized is within a triangle defining a sub-area of the area. The coordinate system in relation to which the triangle is defined is translated such that the pixel co-ordinates are disposed at the origin of the coordinate system. Determinants of matrices based on at least two of the coordinate values of at least two of the vertices are calculated and their signs compared. Based on this comparison a determination as to pixel location with respect to the triangle may be made.

Abstract translation: 计算机图形加速器装置和方法确定正在被光栅化的区域中的预定像素坐标处的像素是否在限定该区域的子区域的三角形之内。 定义三角形相关的坐标系被平移，使得像素坐标设置在坐标系的原点。 计算基于至少两个顶点的至少两个坐标值的矩阵的决定因素并比较它们的符号。 基于该比较，可以进行关于相对于三角形的像素位置的确定。