公开(公告)号：US20250079337A1

公开(公告)日：2025-03-06

申请号：US18460863

申请日：2023-09-05

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Jonghae Kim ,  Bin Yang ,  Giridhar Nallapati

IPC: H01L23/00 ,  H01L21/768 ,  H01L23/48 ,  H01L23/522

Abstract: An integrated circuit (IC) includes a plurality of first metallization layers on a front side of a circuit layer and a plurality of second metallization layers on a back side of the circuit layer. A semiconductor substrate on the back side of the circuit layer of the IC is thinned to improve access to devices from the back side. The plurality of second metallization layers are employed to provide increased interconnection among the devices without increasing area and may provide increased access to external contacts. Thinning the semiconductor substrate reduces structural rigidity needed for processing, so the IC also includes a stiffening layer on one of the plurality of first metallization layers and the plurality of second metallization layers to increase rigidity and first vias extending through the stiffening layer to couple to first contacts.

公开(公告)号：US20240413219A1

公开(公告)日：2024-12-12

申请号：US18333004

申请日：2023-06-12

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Bin Yang ,  Jun Yuan

IPC: H01L29/423 ,  H01L21/8238 ,  H01L27/06 ,  H01L27/092 ,  H01L29/06 ,  H01L29/49 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: Forces applied to the channel regions of semiconductor slabs in a first direction relative to the semiconductor slab, can create strains in the crystal structure that improve carrier mobility to improve drive strength in the channel region. In a three-dimensional (3D) FET structure, a work function metal layer is provided on opposing faces of semiconductor slabs to cause a force to be exerted on the channel regions in a first direction corresponding to current flow. The force in the first direction is either tensile force or compressive force, depending on a FET type (N or P) employing the semiconductor slab, and is provided to create strain in a crystalline structure of the semiconductor slab to improve carrier mobility in the channel region. Increasing carrier mobility in the channel regions in a 3D FET structure increases drive strength of the 3D FET, which saves area in an integrated circuit.

公开(公告)号：US20240355747A1

公开(公告)日：2024-10-24

申请号：US18304195

申请日：2023-04-20

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  John Holmes ,  Aniket Patil ,  Bin Yang

IPC: H01L23/538 ,  H01L21/48 ,  H01L23/00 ,  H01L23/31 ,  H01L25/16 ,  H01L25/18 ,  H10B80/00

CPC classification number: H01L23/5383 ,  H01L21/481 ,  H01L23/3128 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L25/16 ,  H01L25/18 ,  H10B80/00 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/16225 ,  H01L2224/19 ,  H01L2224/211 ,  H01L2224/32225 ,  H01L2224/73204

Abstract: Substrate with multiple core layers to provide varied thickness cavities supporting varied thickness embedded electrical devices, and related integrated circuit (IC) packages and fabrication methods. To provide for core layer of the substrate to support multiple embedded electrical devices, multiple core layers are provided in the substrate. Providing multiple core layers in the substrate allows multiple cavities to be formed in the core layers at multiple depths to compatibly support embedding of multiple electrical devices of varied thicknesses in the core layers. Thus, providing multiple core layers in the substrate can compatibly support forming cavities of multiple thicknesses that are compatible with multiple electrical devices of different thicknesses to be embedded therein. In this manner, design parameters of the overall thickness of the core layer of a substrate can be independent of the variation in thicknesses of multiple embedded electrical devices desired to be embedded therein.

公开(公告)号：US20240047455A1

公开(公告)日：2024-02-08

申请号：US17818048

申请日：2022-08-08

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Bin Yang

IPC: H01L27/06 ,  H01L21/8238 ,  H03K19/0948

CPC classification number: H01L27/0688 ,  H01L21/823871 ,  H03K19/0948

Abstract: A monolithic 3D complementary field-effect transistor (FET) (CFET) circuit includes a first CFET structure and a second CFET structure in a logic circuit within a device layer. A first interconnect layer disposed on the device layer provides first and second input contacts and an output contact of a logic circuit. Each CFET structure includes an upper FET having a first type (e.g., P-type or N-type) on a lower FET having a second type (e.g., N-type or P-type). The FETs in the monolithic 3D CFET circuit may be interconnected to form a two-input NOR circuit or a two-input NAND circuit. Vertical access interconnects (vias) may be formed within the device layer to interconnect the FETs externally and to each other. The FETs may be formed as bulk-type transistors or SOI transistors.

公开(公告)号：US11881862B2

公开(公告)日：2024-01-23

申请号：US17404919

申请日：2021-08-17

Applicant: QUALCOMM Incorporated

Inventor： Udayakiran Kumar Yallamaraju ,  Xia Li ,  Pankaj Deshmukh ,  Vajram Ghantasala ,  Bin Yang ,  Vishal Mishra ,  Bharatheesha Sudarshan Jagirdar ,  Arun Sundaresan Iyer ,  Amod Phadke ,  Vanamali Bhat

IPC: H03K5/156 ,  H03K5/134 ,  H03K19/20 ,  H03K5/00

CPC classification number: H03K5/1565 ,  H03K5/134 ,  H03K19/20 ,  H03K2005/00195

Abstract: A system includes a first park circuit having a signal input, an output, and a control input. The system also includes a first signal path having an input and an output, wherein the input of the first signal path is coupled to the output of the first park circuit. The system also includes a second park circuit having a signal input, an output, and a control input, wherein the signal input of the second park circuit is coupled to the output of the first signal path. The system further includes a second signal path having an input and an output, wherein the input of the second signal path is coupled to the output of the second park circuit.

公开(公告)号：US11689203B1

公开(公告)日：2023-06-27

申请号：US17655697

申请日：2022-03-21

Applicant: QUALCOMM Incorporated

Inventor： Kalyan Kumar Oruganti ,  Rajesh Arimilli ,  Sandeep Aggarwal ,  Gnana Chaitanya Prakash Kopparapu ,  Giby Samson ,  Xia Li

IPC: H03K19/17736 ,  H03K3/0233 ,  H03K3/017 ,  H03K19/173

CPC classification number: H03K19/1774 ,  H03K3/017 ,  H03K3/0233 ,  H03K19/1737

Abstract: In certain aspects, an apparatus includes a gating circuit having an enable input, a signal input, and an output, wherein the enable input is configured to receive an enable signal. The apparatus also includes a toggle circuit having an output, wherein the toggle circuit is configured to toggle a logic state at the output of the toggle circuit based on the enable signal. The apparatus further includes a multiplexer having a first input, a second input, and an output, wherein the first input of the multiplexer is coupled to the output of the gating circuit, the second input of the multiplexer is coupled to the output of the toggle circuit. The multiplexer is configured to select one of the first input and the second input based on the enable signal, and couple the selected one of the first input and the second input to the output of the multiplexer.

公开(公告)号：US20230085846A1

公开(公告)日：2023-03-23

申请号：US17480881

申请日：2021-09-21

Applicant: QUALCOMM Incorporated

Inventor： Xia Li

IPC: H01L23/522 ,  H01L21/768 ,  H01L49/02 ,  H01L23/528 ,  H01L23/66

Abstract: A three-dimensional (3D) metal-insulator-metal capacitor (MIMCAP) includes a plurality of center studs disposed within cavity walls of a plurality of cavities in a top plate. The center studs and the cavity walls are oriented orthogonal to a first metal layer and extend through a first via layer and a second metal layer. Each center stud includes a metal layer stud in the second metal layer stacked on a via layer stud in the first via layer. A dielectric layer is disposed between the center studs and the cavity walls of the plurality of cavities in the top plate. The center studs are coupled to a first electrode, and the top plate is coupled to a second electrode in the interconnect layers. In some examples, the center studs can form vertically oriented cylindrical capacitive elements positioned for high capacitance density.

公开(公告)号：US11533045B1

公开(公告)日：2022-12-20

申请号：US17652092

申请日：2022-02-22

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Min Chen ,  Jianguo Yao ,  Bin Yang

IPC: H03K3/017 ,  H03K5/134 ,  H03K5/00

Abstract: In certain aspects, a duty-cycle monitor includes a first oscillator, and a flop having a signal input, a clock input, and an output, wherein the signal input is coupled to an input of the duty-cycle monitor, and the clock input is coupled to the first oscillator. The duty-cycle monitor also includes a first counter having a count input, an enable input, and a count output, wherein the count input of the first counter is coupled to the first oscillator, and the enable input of the first counter is coupled to the output of the flop. The duty-cycle monitor also includes a second counter having a count input, an enable input, and a count output, wherein the count input of the second counter is coupled to the first oscillator, and the enable input of the second counter is coupled to the output of the flop.

公开(公告)号：US20220271162A1

公开(公告)日：2022-08-25

申请号：US17180219

申请日：2021-02-19

Applicant: QUALCOMM Incorporated

Inventor： Bin Yang ,  Xia Li ,  Haining Yang

IPC: H01L29/78 ,  H01L29/161 ,  H01L27/092 ,  H01L29/66 ,  H01L21/8238

Abstract: An exemplary high performance P-type field-effect transistor (PFET) fabricated on a silicon (Si) germanium (Ge)(SiGe) buffer layer with a SiGe source and drain having a Ge percentage higher than a threshold that causes dislocations at a Si substrate interface is disclosed. A source and drain including a Ge percentage above a 45% threshold provide increased compressive strain in the channel for higher performance of the PFET. Dislocations are avoided in the lattices of the source and drain by forming the PFET on a SiGe buffer layer rather than directly on a Si substrate and the SiGe buffer layer has a percentage of Ge less than a percentage of Ge in the source and drain. In one example, a lattice of the buffer layer is relaxed by implanting dislocations at an interface of the buffer layer and the Si substrate and annealing the buffer layer.

公开(公告)号：US11322199B1

公开(公告)日：2022-05-03

申请号：US17067205

申请日：2020-10-09

Applicant: QUALCOMM Incorporated

Inventor： Xia Li

IPC: G11C11/419 ,  G11C11/409 ,  G11C11/404

Abstract: A CIM bit cell circuit employing a capacitive storage circuit to store a binary weight data as a voltage occupies half or less of the area of a 6T SRAM CIM bit cell circuit, reducing the increase in area incurred in the addition of a CIM bit cell array circuit to an IC. The CIM bit cell circuit includes a capacitive storage circuit that stores binary weight data in a capacitor and generates a product voltage indicating a binary product resulting from a logical AND-based operation of the stored binary weight data and an activation signal. The capacitive storage circuit may include a capacitor and a read access switch or a transistor. The CIM bit cell circuit includes a write access switch to couple a write bit voltage to the capacitive storage circuit. In a CIM bit cell array circuit, the product voltages are summed in a MAC operation.