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    CLOCK TREE DESIGN METHODS FOR ULTRA-WIDE VOLTAGE RANGE CIRCUITS
    3.
    发明申请
    CLOCK TREE DESIGN METHODS FOR ULTRA-WIDE VOLTAGE RANGE CIRCUITS 审中-公开
    用于超宽电压范围电路的时钟树设计方法

    公开(公告)号：US20160267214A1

    公开(公告)日：2016-09-15

    申请号：US14643096

    申请日：2015-03-10

    Applicant: QUALCOMM Incorporated

    Inventor： Sung Kyu Lim ,  Francois Ibrahim Atallah ,  Rashid Ahmed Akbar Attar ,  Keith Alan Bowman ,  Yang Du ,  Juzer Zainuddin Fatehi ,  Jai Ganesh Kumar ,  Yu Pu ,  Giby Samson ,  Kendrick Hoy Leong Yuen

    IPC: G06F17/50

    CPC classification number: G06F17/5081 ,  G06F17/5031 ,  G06F17/5036 ,  G06F2217/62 ,  G06F2217/84

    Abstract: Clock tree design methods for ultra-wide voltage range circuits are disclosed. In one aspect, place and route software creates an integrated circuit (IC) in an optimal configuration at a first voltage condition. A first clock tree is created as part of the place and route process. Clock skew for the first clock tree is evaluated and minimized through insertion of bypassable delay elements. The delay elements are then removed from the wiring routing diagram. A second voltage condition is identified, and clock tree generation software is allowed to optimize the wiring routing diagram for the second voltage condition. The second clock tree generation software may insert more bypassable delay elements into the wiring routing diagram that allow clock skew optimization at the second voltage condition. The initial bypassable delay elements are then reinserted into the wiring routing diagram and a finished IC is established.

    Abstract translation: 公开了用于超宽电压范围电路的时钟树设计方法。 在一个方面，放置和路由软件在第一电压条件下以最佳配置创建集成电路（IC）。 第一个时钟树是作为地点和路由过程的一部分而创建的。 通过插入可旁路延迟元件来评估和最小化第一个时钟树的时钟偏移。 然后将延迟元件从布线图中删除。 识别出第二电压条件，并允许时钟树生成软件优化第二电压条件的布线布线图。 第二个时钟树生成软件可以在布线布线图中插入更多的可旁路延迟元件，允许在第二电压条件下进行时钟偏移优化。 然后将初始可旁路延迟元件重新插入到布线布线图中，并建立成品IC。

    Area and power efficient switchable supply network for powering multiple digital islands
    5.
    发明授权
    Area and power efficient switchable supply network for powering multiple digital islands 有权

    公开(公告)号：US09819189B2

    公开(公告)日：2017-11-14

    申请号：US14843983

    申请日：2015-09-02

    Applicant: QUALCOMM Incorporated

    Inventor： Chunlei Shi ,  Yu Pu ,  Kenneth David Easton ,  Kendrick Hoy Leong Yuen ,  Giby Samson

    IPC: G06F1/32 ,  H02J3/38 ,  H03K19/00

    CPC classification number: H02J3/38 ,  G06F1/3287 ,  H02J2003/388 ,  H03K19/0016

    Abstract: A switchable supply network for powering multiple digital islands. In one embodiment, a first digital island includes a first power collapsible circuit and a first retention circuit, and a second digital island includes a second power collapsible circuit and a second retention circuit. In a normal mode of operation, the first digital island is provided a first supply voltage and a second digital island is provided a second supply voltage higher than the first supply voltage. In a transition mode the second power collapsible circuit is powered down and the second supply voltage is lowered and provided to the second retention circuit. When the second supply voltage falls below the first supply voltage, the first power collapsible circuit is powered down. The second supply voltage is now provided only to the retention circuits, and is furthered lowered in a retention mode to a final retention voltage.

    Ultra-low-power design memory power reduction scheme
    6.
    发明授权
    Ultra-low-power design memory power reduction scheme 有权

    公开(公告)号：US10539997B2

    公开(公告)日：2020-01-21

    申请号：US15255176

    申请日：2016-09-02

    Applicant: QUALCOMM Incorporated

    Inventor： Giby Samson ,  Parixit Laljibhai Aghera ,  Adam Edward Newham

    IPC: G06F1/32 ,  G06F1/3287 ,  G06F1/3296

    Abstract: The disclosure generally relates to a memory power reduction scheme that can flexibly transition memory blocks among different power states to reduce power consumption (especially with respect to leakage power) in a manner that balances tradeoffs between reduced power consumption and performance impacts. For example, according to various aspects, individual memory blocks may be associated with an access-dependent age, whereby memory blocks that are not accessed may be periodically aged. As such, in response to the age associated with a memory block crossing an appropriate threshold, the memory block may be transitioned to a power state that generally consumes less leakage power and has a larger performance penalty. Furthermore, one or more performance-related criteria may be defined with certain memory blocks to prevent and/or automatically trigger a transition to another power state.

    Single-ended contention-free wide operating range level voltage shifter with built-in voltage boosting and down-stepping assisting circuitry
    7.
    发明授权
    Single-ended contention-free wide operating range level voltage shifter with built-in voltage boosting and down-stepping assisting circuitry 有权
    具有内置升压和下行辅助电路的单端无争用宽工作范围电平转换器

    公开(公告)号：US09515660B1

    公开(公告)日：2016-12-06

    申请号：US14843992

    申请日：2015-09-02

    Applicant: QUALCOMM Incorporated

    Inventor： Giby Samson ,  Yu Pu ,  Kendrick Hoy Leong Yuen

    IPC: H03K19/0185 ,  H03K17/687

    CPC classification number: H03K19/018507

    Abstract: A voltage level shifter to provide an output logic signal in response to an input logic signal, where the input logic signal is in a first voltage domain and the output logic signal is in a second voltage domain. In one embodiment, a voltage boost module provides a boosted voltage in response to the input logic signal going HIGH, where the boosted voltage is sufficient to turn OFF a pull-up transistor operating in the second voltage domain. Contention among pull-down and pull-up transistors may be avoided.

    Abstract translation: 电压电平移位器，用于响应于输入逻辑信号提供输出逻辑信号，其中输入逻辑信号处于第一电压域，并且输出逻辑信号处于第二电压域。 在一个实施例中，电压升压模块响应于输入逻辑信号变为高电平而提供升压电压，其中升压电压足以关闭在第二电压域中工作的上拉晶体管。 可以避免下拉和上拉晶体管之间的争用。

    CLOCK DISTRIBUTION SCHEMES WITH WIDE OPERATING VOLTAGE RANGES
    8.
    发明申请
    CLOCK DISTRIBUTION SCHEMES WITH WIDE OPERATING VOLTAGE RANGES 审中-公开
    具有宽操作电压范围的时钟分配方案

    公开(公告)号：US20160269009A1

    公开(公告)日：2016-09-15

    申请号：US14642859

    申请日：2015-03-10

    Applicant: QUALCOMM Incorporated

    Inventor： Giby Samson ,  Yu Pu ,  Kendrick Hoy Leong Yuen

    IPC: H03K5/135 ,  G06F1/10

    CPC classification number: H03K5/135 ,  G06F1/10 ,  H03K19/0016 ,  H03K2005/00052

    Abstract: Clock distribution schemes with wide operating voltage ranges are disclosed. In one aspect, an operating voltage level or condition within a computing device is sensed. In a first voltage condition, delay elements are used within a clock tree to minimize clock skew. In a second voltage condition, one or more delay and/or clocked elements are bypassed to minimize clock skew at the second voltage condition. In addition to controlling clock skew, power may be conserved by depowering the bypassed elements. Controlling clock skew in this fashion improves operation of a computing device that includes the clock tree and may improve battery life.

    Abstract translation: 公开了具有宽工作电压范围的时钟分配方案。 在一个方面，感测计算设备内的工作电压电平或状况。 在第一电压条件下，在时钟树中使用延迟元件以最小化时钟偏移。 在第二电压条件下，绕过一个或多个延迟和/或时钟元件以使在第二电压条件下的时钟偏移最小化。 除了控制时钟偏移之外，通过削弱旁路元件可以节省功率。 以这种方式控制时钟偏移改善了包括时钟树的计算设备的操作并且可以提高电池寿命。

    Digital design with bundled data asynchronous logic and body-biasing tuning
    9.
    发明授权
    Digital design with bundled data asynchronous logic and body-biasing tuning 有权

    公开(公告)号：US10552563B2

    公开(公告)日：2020-02-04

    申请号：US15866876

    申请日：2018-01-10

    Applicant: QUALCOMM Incorporated

    Inventor： Mark Lin ,  Yu Pu ,  Giby Samson

    IPC: G06F17/50 ,  H03K19/00 ,  H01L25/00

    Abstract: Aspects of the disclosure are directed to a digital design with bundled data asynchronous logic and body-biasing tuning. In one aspect, implementation includes establishing a control path between a first controller and a second controller using a handshaking protocol; establishing a data path between a first latch and a second latch using a bundled data technique; executing a first dynamic body biasing tuning by applying a first body bias signal to the control path; executing a second dynamic body biasing tuning by applying a second body bias signal to the data path. The digital design includes a first controller with a control path to connect to a second controller, wherein a first body bias tuning signal tunes body bias in the control path, a first latch with a data path to connect to a second latch, wherein a second body bias tuning signal tunes body bias in the data path.

    Electronic devices employing adiabatic logic circuits with wireless charging
    10.
    发明授权
    Electronic devices employing adiabatic logic circuits with wireless charging 有权

    公开(公告)号：US10432197B2

    公开(公告)日：2019-10-01

    申请号：US15230885

    申请日：2016-08-08

    Applicant: QUALCOMM Incorporated

    Inventor： Yu Pu ,  Giby Samson

    IPC: H03K19/00 ,  H02J7/02 ,  H02J50/10 ,  H03K19/017

    Abstract: Electronic devices employing adiabatic logic circuits with wireless charging are disclosed. In one aspect, an electronic device is provided. The electronic device includes a power circuit employing an alternating current (AC) coupler circuit configured to receive a wireless AC signal and generate a wired AC signal based on the wireless AC signal. The power circuit includes a power output configured to provide an AC power signal based on the wired AC signal generated by the AC coupler circuit. The AC power signal is generated based on the wireless charging capability of the AC coupler circuit. The electronic device employs a digital logic system that includes a power rail electrically coupled to an adiabatic logic circuit. The AC power signal is provided to the power rail to provide power to the adiabatic logic circuit. Wirelessly charging the adiabatic logic circuit consumes less power than conventional non-wireless charging circuitry.

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