公开(公告)号：US11249759B2

公开(公告)日：2022-02-15

申请号：US16420457

申请日：2019-05-23

Applicant: Texas Instruments Incorporated

Inventor： William Franklin Leven ,  Asheesh Bhardwaj ,  Son Hung Tran ,  Timothy David Anderson

IPC: G06F9/34 ,  G06F11/00 ,  G06F12/0875 ,  G06F17/16 ,  G06F9/30 ,  G06F9/38 ,  G06F11/10 ,  G06F9/32 ,  G06F12/0897 ,  G06F9/345

Abstract: Software instructions are executed on a processor within a computer system to configure a steaming engine with stream parameters to define a multidimensional array. The stream parameters define a size for each dimension of the multidimensional array and a specified width for two selected dimensions of the array. Data is fetched from a memory coupled to the streaming engine responsive to the stream parameters. A stream of vectors is formed for the multidimensional array responsive to the stream parameters from the data fetched from memory. When either selected dimension in the stream of vectors exceeds a respective specified width, the streaming engine inserts null elements into each portion of a respective vector for the selected dimension that exceeds the specified width in the stream of vectors. Stream vectors that are completely null are formed by the streaming engine without accessing the system memory for respective data.

公开(公告)号：US20210406014A1

公开(公告)日：2021-12-30

申请号：US17472877

申请日：2021-09-13

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Joseph Raymond Michael Zbiciak ,  Timothy David Anderson ,  Jonathan (Son) Hung Tran ,  Kai Chirca ,  Daniel Wu ,  Abhijeet Ashok Chachad ,  David M. Thompson

IPC: G06F9/30 ,  G06F9/345 ,  G06F12/0875 ,  G06F9/38 ,  G06F9/32 ,  G06F12/0897 ,  G06F11/10 ,  G06F11/00 ,  G06F12/0831 ,  G06F12/1027

Abstract: A stream of data is accessed from a memory system using a stream of addresses generated in a first mode of operating a streaming engine in response to executing a first stream instruction. A block cache management operation is performed on a cache in the memory using a block of addresses generated in a second mode of operating the streaming engine in response to executing a second stream instruction.

公开(公告)号：US20210344361A1

公开(公告)日：2021-11-04

申请号：US17378886

申请日：2021-07-19

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Dheera Balasubramanian ,  Joseph Zbiciak ,  Duc Quang Bui ,  Timothy David Anderson

IPC: H03M13/00 ,  H03M13/27 ,  G06F9/38

Abstract: A method is shown that is operable to transform and align a plurality of fields from an input to an output data stream using a multilayer butterfly or inverse butterfly network. Many transformations are possible with such a network which may include separate control of each multiplexer. This invention supports a limited set of multiplexer control signals, which enables a similarly limited set of data transformations. This limited capability is offset by the reduced complexity of the multiplexor control circuits.

公开(公告)号：US11074193B2

公开(公告)日：2021-07-27

申请号：US16551587

申请日：2019-08-26

Applicant: Texas Instruments Incorporated

Inventor： Timothy David Anderson ,  Mujibur Rahman ,  Dheera Balasubramanian Samudrala ,  Peter Richard Dent ,  Duc Quang Bui

IPC: G06F9/315 ,  G06F12/0875 ,  G06F11/00 ,  G06F15/76 ,  G06F12/1045 ,  G06F9/30 ,  G06F9/345 ,  G06F9/38 ,  G06F11/10 ,  G06F9/32 ,  G06F12/0897 ,  G06F12/0862 ,  G06F12/1009 ,  G06F15/78

Abstract: A method is provided that includes performing, by a processor in response to a vector permutation instruction, permutation of values stored in lanes of a vector to generate a permuted vector, wherein the permutation is responsive to a control storage location storing permute control input for each lane of the permuted vector, wherein the permute control input corresponding to each lane of the permuted vector indicates a value to be stored in the lane of the permuted vector, wherein the permute control input for at least one lane of the permuted vector indicates a value of a selected lane of the vector is to be stored in the at least one lane, and storing the permuted vector in a storage location indicated by an operand of the vector permutation instruction.

公开(公告)号：US20210224065A1

公开(公告)日：2021-07-22

申请号：US17213509

申请日：2021-03-26

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Timothy David Anderson ,  Jonathan (Son) Hung Tran ,  Joseph Raymond Michael Zbiciak

IPC: G06F9/30 ,  G06F9/38 ,  G06F11/10 ,  G06F9/32 ,  G06F12/0875 ,  G06F12/0897 ,  G06F11/00 ,  G06F9/345

Abstract: A steaming engine in a system receives a first set of stream parameters into a queue to define a first stream along with an indication of either a queue mode of operation or a speculative mode of operation for the first stream. Acquisition of the first stream then begins. At some point, a second set of stream parameters is received into the queue to define a second stream. When the queue mode of operation was specified for the first stream, the second set of parameters is queued and acquisition of the second stream is delayed until completion of acquisition of the first stream. When the speculative mode of operation was specified for the first stream, acquisition of the first stream is canceled upon receipt of the second set of stream parameters and acquisition of the second stream begins immediately.

公开(公告)号：US20200371960A1

公开(公告)日：2020-11-26

申请号：US16882244

申请日：2020-05-22

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Naveen Bhoria ,  Timothy David Anderson ,  Pete Michael Hippleheuser

IPC: G06F12/128 ,  G06F12/0897

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed for allocation in a victim cache system. An example apparatus includes a first cache storage, a second cache storage, a cache controller coupled to the first cache storage and the second cache storage and operable to receive a memory operation that specifies an address, determine, based on the address, that the memory operation evicts a first set of data from the first cache storage, determine that the first set of data is unmodified relative to an extended memory, and cause the first set of data to be stored in the second cache storage.

公开(公告)号：US20200371957A1

公开(公告)日：2020-11-26

申请号：US16882241

申请日：2020-05-22

Applicant: Texas Instruments Incorporated

Inventor： Naveen Bhoria ,  Timothy David Anderson ,  Pete Michael Hippleheuser

IPC: G06F12/12 ,  G06F12/0895

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed for multi-banked victim cache with dual datapath. An example cache system includes a storage element that includes banks operable to store data, ports operable to receive memory operations in parallel, wherein each of the memory operations has a respective address, and a plurality of comparators coupled such that each of the comparators is coupled to a respective port of the ports and a respective bank of the banks and is operable to determine whether a respective address of a respective memory operation received by the respective port corresponds to the data stored in the respective bank.

公开(公告)号：US20200371949A1

公开(公告)日：2020-11-26

申请号：US16882262

申请日：2020-05-22

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Naveen Bhoria ,  Timothy David Anderson ,  Pete Michael Hippleheuser

IPC: G06F12/0888 ,  G06F12/0891 ,  G06F9/30 ,  G06F9/54 ,  G11C7/10 ,  G11C29/42 ,  G11C29/44

Abstract: Methods, apparatus, systems and articles of manufacture to facilitate atomic operation in victim cache are disclosed. An example system includes a first cache storage to store a first set of data; a second cache storage to store a second set of data that has been evicted from the first cache storage; and a storage queue coupled to the first cache storage and the second cache storage, the storage queue including: an arithmetic component to: receive the second set of data from the second cache storage in response to a memory operation; and perform an arithmetic operation on the second set of data to produce a third set of data; and an arbitration manager to store the third set of data in the second cache storage.

公开(公告)号：US20200371939A1

公开(公告)日：2020-11-26

申请号：US16882238

申请日：2020-05-22

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Naveen Bhoria ,  Timothy David Anderson ,  Pete Michael Hippleheuser

IPC: G06F12/0855 ,  G06F11/10 ,  G06F12/12

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to facilitate fully pipelined read-modify-write support in level 1 data cache using store queue and data forwarding. An example apparatus includes a first storage, a second storage, a store queue coupled to the first storage and the second storage, the store queue operable to receive a first memory operation specifying a first set of data, process the first memory operation for storing the first set of data in at least one of the first storage and the second storage, receive a second memory operation, and prior to storing the first set of data in the at least one of the first storage and the second storage, feedback the first set of data for use in the second memory operation.

公开(公告)号：US20200371937A1

公开(公告)日：2020-11-26

申请号：US16879264

申请日：2020-05-20

Applicant: Texas Instruments Incorporated

Inventor： Abhijeet Ashok Chachad ,  Timothy David Anderson ,  Kai Chirca ,  David Matthew Thompson

IPC: G06F12/0842 ,  G06F12/0888 ,  G06F12/0811

Abstract: In described examples, a processor system includes a processor core generating memory transactions, a lower level cache memory with a lower memory controller, and a higher level cache memory with a higher memory controller having a memory pipeline. The higher memory controller is connected to the lower memory controller by a bypass path that skips the memory pipeline. The higher memory controller: determines whether a memory transaction is a bypass write, which is a memory write request indicated not to result in a corresponding write being directed to the higher level cache memory; if the memory transaction is determined a bypass write, determines whether a memory transaction that prevents passing is in the memory pipeline; and if no transaction that prevents passing is determined to be in the memory pipeline, sends the memory transaction to the lower memory controller using the bypass path.