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公开(公告)号：US09489262B2
公开(公告)日：2016-11-08
申请号：US15018762
申请日：2016-02-08
Inventor： Sung-Ik Park , Heung-Mook Kim , Sun-Hyoung Kwon , Nam-Ho Hur
CPC classification number: H03M13/1165 , G06F11/1076 , H03M13/036 , H03M13/1102 , H03M13/616 , H04L1/0043 , H04L1/0057
Abstract: A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 16200 and a code rate of 2/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM).
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公开(公告)号：US12047095B2
公开(公告)日：2024-07-23
申请号：US18314938
申请日：2023-05-10
Inventor： Sung-Ik Park , Sun-Hyoung Kwon , Jae-Young Lee , Heung-Mook Kim
CPC classification number: H03M13/152 , H03M13/116 , H03M13/1162 , H03M13/1165 , H03M13/271 , H03M13/2778 , H03M13/618 , H03M13/6362 , H03M13/253 , H03M13/255 , H03M13/2906 , H03M13/6393 , H03M13/6552
Abstract: A parity interleaving apparatus and method for variable length signaling information are disclosed. A parity interleaving apparatus according to an embodiment of the present invention includes a processor configured to generate a parity bit string for parity puncturing by segmenting parity bits of an LDPC codeword whose length is 16200 and whose code rate is 3/15, into a plurality of groups, and group-wise interleaving the groups using an order of group-wise interleaving; and memory configured to provide the parity bit string for parity puncturing to a parity puncturing unit.
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213.发明授权公开(公告)号：US11943090B2
公开(公告)日：2024-03-26
申请号：US17379820
申请日：2021-07-19
Inventor： Sung-Ik Park , Jae-Young Lee , Sun-Hyoung Kwon , Heung-Mook Kim , Nam-Ho Hur
CPC classification number: H04L27/2697 , H03M13/25 , H03M13/27 , H04L1/00 , H04L1/0041 , H04L1/0048 , H04L1/0061 , H04L1/0071 , H04L5/0007 , H04L2001/0098 , H04L27/2601
Abstract: An apparatus and method for multiplexing signals using layered division multiplexing are disclosed. A signal multiplexing apparatus according to an embodiment of the present invention includes a combiner configured to combine a core layer signal and an enhanced layer signal at different power levels, and a time interleaver configured to perform interleaving applied to both the core layer signal and the enhanced layer signal.
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公开(公告)号：US11770136B2
公开(公告)日：2023-09-26
申请号：US17391991
申请日：2021-08-02
Inventor： Sung-Ik Park , Sun-Hyoung Kwon , Jae-Young Lee , Heung-Mook Kim , Nam-Ho Hur
CPC classification number: H03M13/1165 , H03M13/255 , H03M13/271 , H03M13/2778
Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 2/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 4096-symbol mapping.
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公开(公告)号：US11711156B2
公开(公告)日：2023-07-25
申请号：US17700751
申请日：2022-03-22
Inventor： Sung-Ik Park , Sun-Hyoung Kwon , Jae-Young Lee , Heung-Mook Kim , Nam-Ho Hur
IPC: H04H20/67 , H04H20/31 , H04H20/71 , H04H60/44 , H04H60/73 , H04J11/00 , H04L1/00 , H04L27/26 , H04L69/323 , H04W52/32 , H04H20/72 , H04W52/34
CPC classification number: H04H20/67 , H04H20/31 , H04H20/71 , H04H60/44 , H04H60/73 , H04J11/004 , H04L1/0041 , H04L1/0045 , H04L1/0057 , H04L1/0065 , H04L1/0071 , H04L27/2613 , H04L27/2627 , H04L69/323 , H04W52/322 , H04H20/72 , H04L27/2605 , H04L27/2626 , H04W52/346
Abstract: An apparatus for transmitting broadcasting signal using transmitter identification scaled by 4-bit injection level code and method using the same are disclosed. An apparatus for transmitting broadcasting signal according to an embodiment of the present invention includes a waveform generator configured to generate a host broadcasting signal; a transmitter identification signal generator configured to generate a transmitter identification signal for identifying a transmitter, the transmitter identification signal scaled by an injection level code; and a combiner configured to inject the transmitter identification signal into the host broadcasting signal in a time domain so that the transmitter identification signal is transmitted synchronously with the host broadcasting signal.
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Patent Agency Ranking
公开(公告)号：US11711096B2
公开(公告)日：2023-07-25
申请号：US17835651
申请日：2022-06-08
Inventor： Sung-Ik Park , Heung-Mook Kim , Sun-Hyoung Kwon , Nam-Ho Hur
CPC classification number: H03M13/1157 , H03M13/036 , H03M13/1165 , H03M13/1185 , H03M13/616 , H03M13/2792 , H03M13/6552 , H04L1/0041 , H04L1/0043 , H04L1/0057 , H04L1/0058 , H04L1/0071
Abstract: A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 16200 and a code rate of 3/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM).
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公开(公告)号：US11695433B2
公开(公告)日：2023-07-04
申请号：US17522990
申请日：2021-11-10
Inventor： Sung-Ik Park , Sun-Hyoung Kwon , Jae-Young Lee , Heung-Mook Kim
CPC classification number: H03M13/2792 , H03M13/255 , H03M13/2778 , H03M13/618 , H04L1/0068 , H03M13/1148 , H03M13/1165 , H03M13/152 , H03M13/253 , H03M13/2906 , H03M13/6362 , H04L1/0041 , H04L1/0058 , H04L1/0071
Abstract: A parity interleaving apparatus and method for fixed length signaling information are disclosed. A parity interleaving apparatus according to an embodiment of the present invention includes a processor configured to generate a parity bit string for parity puncturing by segmenting parity bits of an LDPC codeword whose length is 16200 and whose code rate is 3/15, into a plurality of groups, and group-wise interleaving the groups using an order of group-wise interleaving; and memory configured to provide the parity bit string for parity puncturing to a parity puncturing unit.
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公开(公告)号：US11677421B2
公开(公告)日：2023-06-13
申请号：US17845614
申请日：2022-06-21
Inventor： Sung-Ik Park , Sun-Hyoung Kwon , Jae-Young Lee , Heung-Mook Kim , Nam-Ho Hur
CPC classification number: H03M13/2757 , H03M13/1102 , H03M13/116 , H03M13/1185 , H03M13/255 , H03M13/2778 , H03M13/2792 , H03M13/616 , H03M13/6552 , H04L1/0041 , H04L1/0057 , H04L1/0058 , H04L1/0071 , H04L27/20 , H04L27/3416
Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 7/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for quadrature phase shift keying (QPSK) modulation.
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公开(公告)号：US11652853B2
公开(公告)日：2023-05-16
申请号：US17314276
申请日：2021-05-07
Inventor： Hoi-Yoon Jung , Sung-Ik Park , Heung-Mook Kim , Nam-Ho Hur , David Gomez-Barquero , Eduardo Garro , Carlos Barjau Estevan
IPC: H04L65/1023 , H04L65/1069 , H04W28/08 , H04L65/80
CPC classification number: H04L65/1023 , H04L65/1069 , H04L65/80 , H04W28/0819
Abstract: Disclosed herein is an integrated core network of 5G and ATSC 3.0. The integrated core network of 5G and ATSC 3.0 includes multiple control plane entities and a user plane entity, and further includes an ATSC 3.0 gateway, thereby enabling multimedia content transmitted from the ATSC 3.0 gateway to the user plane entity under the control of the control entity to be delivered to user equipment over an ATSC 3.0 terrestrial network. The ATSC 3.0 gateway may include an ATSC 3.0 Control Plane Gateway (CP-GW) connected between the user plane entity and the multiple control plane entities and an ATSC 3.0 User Plane Gateway (UP-GW) connected to the user plane entity.
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公开(公告)号：US11646752B2
公开(公告)日：2023-05-09
申请号：US17479763
申请日：2021-09-20
Inventor： Sung-Ik Park , Sun-Hyoung Kwon , Jae-Young Lee , Heung-Mook Kim , Nam-Ho Hur
CPC classification number: H03M13/1165 , H03M13/255 , H03M13/271 , H03M13/2778
Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 4/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 4096-symbol mapping.
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