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    COMPUTE-IN-MEMORY (CIM) CELL CIRCUITS EMPLOYING CAPACITIVE STORAGE CIRCUITS FOR REDUCED AREA AND CIM BIT CELL ARRAY CIRCUITS
    211.
    发明申请
    COMPUTE-IN-MEMORY (CIM) CELL CIRCUITS EMPLOYING CAPACITIVE STORAGE CIRCUITS FOR REDUCED AREA AND CIM BIT CELL ARRAY CIRCUITS 有权

    公开(公告)号：US20220115059A1

    公开(公告)日：2022-04-14

    申请号：US17067205

    申请日：2020-10-09

    Applicant: QUALCOMM Incorporated

    Inventor： Xia Li

    IPC: G11C11/419 ,  G11C11/404 ,  G11C11/409

    Abstract: A CIM bit cell circuit employing a capacitive storage circuit to store a binary weight data as a voltage occupies half or less of the area of a 6T SRAM CIM bit cell circuit, reducing the increase in area incurred in the addition of a CIM bit cell array circuit to an IC. The CIM bit cell circuit includes a capacitive storage circuit that stores binary weight data in a capacitor and generates a product voltage indicating a binary product resulting from a logical AND-based operation of the stored binary weight data and an activation signal. The capacitive storage circuit may include a capacitor and a read access switch or a transistor. The CIM bit cell circuit includes a write access switch to couple a write bit voltage to the capacitive storage circuit. In a CIM bit cell array circuit, the product voltages are summed in a MAC operation.

    DOUBLE-SIDE BACK-END-OF-LINE METALLIZATION FOR PSEUDO THROUGH-SILICON VIA INTEGRATION
    212.
    发明申请
    DOUBLE-SIDE BACK-END-OF-LINE METALLIZATION FOR PSEUDO THROUGH-SILICON VIA INTEGRATION 有权

    公开(公告)号：US20220020665A1

    公开(公告)日：2022-01-20

    申请号：US16928759

    申请日：2020-07-14

    Applicant: QUALCOMM Incorporated

    Inventor： Xia Li ,  Bin Yang ,  Haining Yang

    IPC: H01L23/48 ,  H01L23/522 ,  H01L25/065 ,  H01L23/528 ,  H01L21/762

    Abstract: Methods, systems, and devices for double side back-end-of-line (BEOL) metallization for pseudo through-silicon via (pTSV) integration are described. An integrated circuit (IC) may include multiple metallic layers integrated within multiple layers of a multi-dimensional integrated stack (e.g., a three dimensional (3D) integrated stack). By performing a BEOL metallization process, the integrated circuit may implement techniques for 3D vertical chip integration. For example, a first set of layers may be formed during a first portion of a BEOL process and a second portion of the BEOL process may integrate a second set of metallic layers as well as a buried power delivery network (PDN). The metallic layers may form a number of pTSVs and may promote a PDN to experience a reduced PDN IR drop. The PDN may be integrated and the pTSVs may be formed by integrating the metallic layers within a number of dielectric layers.

    GATE ALL AROUND TRANSISTORS WITH HIGH CHARGE MOBILITY CHANNEL MATERIALS
    213.
    发明申请
    GATE ALL AROUND TRANSISTORS WITH HIGH CHARGE MOBILITY CHANNEL MATERIALS 有权

    公开(公告)号：US20210226009A1

    公开(公告)日：2021-07-22

    申请号：US16749897

    申请日：2020-01-22

    Applicant: QUALCOMM Incorporated

    Inventor： Bin Yang ,  Haining Yang ,  Xia Li

    IPC: H01L29/10 ,  H01L29/16 ,  H01L29/201 ,  H01L29/43 ,  H01L29/78 ,  H01L29/66

    Abstract: A semiconductor device comprising an N-type metal oxide semiconductor (NMOS) gate-all-around (GAA) transistor and a P-type metal oxide semiconductor (PMOS) GAA transistor with high charge mobility channel materials is disclosed. The semiconductor device may include a substrate. The semiconductor device may also include an NMOS GAA transistor on the substrate, wherein the NMOS GAA transistor comprises a first channel material. The semiconductor device may further include a PMOS GAA transistor on the substrate, wherein the PMOS GAA transistor comprises a second channel material. The first channel material may have an electron mobility greater than an electron mobility of Silicon (Si) and the second channel material may have a hole mobility greater than a hole mobility of Si.

    CIRCUITS EMPLOYING ON-DIFFUSION (OD) EDGE (ODE) DUMMY GATE STRUCTURES IN CELL CIRCUIT WITH INCREASED GATE DIELECTRIC THICKNESS TO REDUCE LEAKAGE CURRENT
    214.
    发明申请
    CIRCUITS EMPLOYING ON-DIFFUSION (OD) EDGE (ODE) DUMMY GATE STRUCTURES IN CELL CIRCUIT WITH INCREASED GATE DIELECTRIC THICKNESS TO REDUCE LEAKAGE CURRENT 有权

    公开(公告)号：US20210118985A1

    公开(公告)日：2021-04-22

    申请号：US17022338

    申请日：2020-09-16

    Applicant: QUALCOMM Incorporated

    Inventor： Xia Li ,  Haining Yang ,  Bin Yang

    IPC: H01L29/06 ,  H01L27/088 ,  H01L21/8234

    Abstract: Circuits employing on-diffusion (OD) edge (ODE) dummy gate structures in cell circuit with increased gate dielectric thickness to reduce leakage current are disclosed. A gate dielectric structure may be formed between a work function metal structure of an ODE dummy gate structure and an active semiconductor structure in a cell circuit, and is provided to be thicker than a gate dielectric structure formed between a work function metal structure and an active gate(s) in the cell circuit. Providing a gate dielectric structure of increased thickness can reduce damage to the gate dielectric structure providing isolation between the ODE dummy gate structure and the active semiconductor structure. Providing a gate dielectric structure of increased thickness can also reduce the gap area adjacent to the ends of the active semiconductor structures and thus reduce the volume of work function metal structure formed in the gaps to further reduce leakage current.

    RESISTIVE RANDOM ACCESS MEMORY (RRAM) DEVICES EMPLOYING BOUNDED FILAMENT FORMATION REGIONS, AND RELATED METHODS OF FABRICATING
    215.
    发明申请
    RESISTIVE RANDOM ACCESS MEMORY (RRAM) DEVICES EMPLOYING BOUNDED FILAMENT FORMATION REGIONS, AND RELATED METHODS OF FABRICATING 审中-公开

    公开(公告)号：US20200328350A1

    公开(公告)日：2020-10-15

    申请号：US16382880

    申请日：2019-04-12

    Applicant: QUALCOMM Incorporated

    Inventor： Bin Yang ,  Xia Li ,  Guoqing Chen

    IPC: H01L45/00 ,  H01L27/24

    Abstract: An RRAM device is disclosed, having reduced area without increased performance variation, formed by employing a bounded filament formation region in which an oxide layer is thinner and an implanted ion concentration is higher than in a peripheral region of the oxide layer surrounding the bounded filament formation region. Filament formation is controlled to occur in a bounded region having a reduced area by thinning the oxide layer in the bounded region to increase an electric field strength in the bounded region. Defects in the bounded region are subject to greater force from the electric field than defects in the peripheral region. By implanting additional mobile ions or other ion species in the bounded region by an accurately controlled process, a higher concentration of defects is introduced into the bounded region to promote filament formation. Memory elements based on the RRAM device are formed at higher density and lower cost.

    TERNARY COMPUTATION MEMORY SYSTEMS AND CIRCUITS EMPLOYING BINARY BIT CELL-XNOR CIRCUITS PARTICULARLY SUITED TO DEEP NEURAL NETWORK (DNN) COMPUTING
    216.
    发明申请
    TERNARY COMPUTATION MEMORY SYSTEMS AND CIRCUITS EMPLOYING BINARY BIT CELL-XNOR CIRCUITS PARTICULARLY SUITED TO DEEP NEURAL NETWORK (DNN) COMPUTING 审中-公开

    公开(公告)号：US20200301668A1

    公开(公告)日：2020-09-24

    申请号：US16360698

    申请日：2019-03-21

    Applicant: QUALCOMM Incorporated

    Inventor： Xia Li

    IPC: G06F7/544 ,  G11C11/412 ,  G11C11/419 ,  G06N3/04

    Abstract: A multiply-accumulate (MAC) operation in a deep neural network (DNN) consists of multiplying each input signal to a node by a respective numerical weight data and summing the products. Using ternary values for the input signals and weight data reduces memory and processing resources significantly. By representing ternary values in two-bit binary form, MAC operations can be replaced with logic operations (e.g., XNOR, popcount) implemented in logic circuits integrated into individual memory array elements in which the numerical weight data are stored. In this regard, a ternary computation circuit (TCC) includes a memory circuit integrated with a logic circuit. A memory array including TCCs performs a plurality of parallel operations (e.g., column or row elements) and determines a popcount. A TCC array in which logic circuits in columns or rows employ a single read-enable signal can reduce routing complexity and congestion of a metal layer in a semiconductor device.

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