公开(公告)号：US20060255371A1

公开(公告)日：2006-11-16

申请号：US11432675

申请日：2006-05-10

Applicant: Francois Roy ,  Arnaud Tournier

Inventor： Francois Roy ,  Arnaud Tournier

IPC: H01L27/148

CPC classification number: H01L27/1443 ,  H01L27/14609

Abstract: An integrated circuit includes at least one photodiode associated with a read transistor. The photodiode is formed from a stack of three semiconductor layers comprising a buried layer, an floating substrate layer and an upper layer. The drain region and/or the source region of the transistor are incorporated within the upper layer. The buried layer is electrically isolated from the upper layer so as to allow the buried layer to be biased independently of the upper layer.

Abstract translation: 集成电路包括与读取晶体管相关联的至少一个光电二极管。 光电二极管由包括掩埋层，浮置衬底层和上层的三个半导体层的堆叠形成。 晶体管的漏极区域和/或源极区域被并入上层。 掩埋层与上层电隔离，以便允许掩埋层独立于上层被偏置。

公开(公告)号：US20060253708A1

公开(公告)日：2006-11-09

申请号：US11431328

申请日：2006-05-10

Applicant: Michel Bardouillet ,  Claude Anguille ,  Joan Daemen

Inventor： Michel Bardouillet ,  Claude Anguille ,  Joan Daemen

IPC: H04L9/00

CPC classification number: G06F21/79

Abstract: A method for recording at least one block of variable data in a first volatile memory external to a microprocessor, including calculating and storing a digital signature taking into account at least partially the address and the content of said data block in the memory, and at least a first random digital value internal to the microprocessor.

Abstract translation: 该方法包括基于易失性存储器中的数据块的地址和内容来计算和存储数字签名，微处理器内部的随机数字值和由微处理器执行的每个新的同步程序修改的数字密钥和/或用于 每次初始化 包括用于检查从微处理器外部的易失性存储器读取的数据块的内容的方法的独立权利要求。

公开(公告)号：US07132765B2

公开(公告)日：2006-11-07

申请号：US10726259

申请日：2003-12-02

Applicant: Christophe Premont ,  Louis Tallaron ,  Severin Trochut

Inventor： Christophe Premont ,  Louis Tallaron ,  Severin Trochut

IPC: H02J1/00

CPC classification number: H02M3/157 ,  H02M3/1584 ,  Y10T307/696 ,  Y10T307/702

Abstract: The switch mode power supply includes a switching cell SC controllable cyclically and including only one inductive element L and several individually selectable outputs. During each conduction cycle, a total power level corresponding to the sum of the individual power levels respectively required by all the outputs OUTi during this cycle is injected into the inductive element L, the outputs requiring a non-zero individual power level are selected successively and in a predetermined order that is identical for all the cycles, and, at each selected output, the corresponding individual power level is produced.

Abstract translation: 开关模式电源包括周期性可控的切换单元SC，并且仅包括一个电感元件L和几个可单独选择的输出。 在每个导通周期期间，对应于在该周期期间所有输出OUTi分别要求的各个功率电平之和的总功率电平被注入到电感元件L中，连续选择需要非零个别功率电平的输出， 以对于所有周期相同的预定顺序，并且在每个选择的输出处产生相应的单独功率电平。

公开(公告)号：US07122879B2

公开(公告)日：2006-10-17

申请号：US10942165

申请日：2004-09-16

Applicant: Alain Chantre ,  Bertrand Martinet ,  Michel Marty ,  Pascal Chevalier

Inventor： Alain Chantre ,  Bertrand Martinet ,  Michel Marty ,  Pascal Chevalier

IPC: H01L27/02 ,  H01L29/70 ,  H01L31/11

CPC classification number: H01L29/66242 ,  H01L21/8249 ,  H01L29/0817 ,  H01L29/36 ,  H01L29/41708 ,  H01L29/42304 ,  H01L29/456 ,  H01L29/7378

Abstract: A bipolar transistor with very high dynamic performance, usable in an integrated circuit. The bipolar transistor has a single-crystal silicon emitter region with a thickness smaller than 50 nm. The base of the bipolar transistor is made of an SiGe alloy.

Abstract translation: 具有非常高动态性能的双极晶体管，可用于集成电路。 双极晶体管具有厚度小于50nm的单晶硅发射极区域。 双极晶体管的基极由SiGe合金制成。

公开(公告)号：US20060226512A1

公开(公告)日：2006-10-12

申请号：US11385044

申请日：2006-03-20

Applicant: Denis Cottin ,  Thierry Schwartzmann ,  Jean-Charles Vildeuil ,  Bertrand Martinet ,  Sophie Taupin ,  Mathieu Marin

Inventor： Denis Cottin ,  Thierry Schwartzmann ,  Jean-Charles Vildeuil ,  Bertrand Martinet ,  Sophie Taupin ,  Mathieu Marin

IPC: H01L29/00

CPC classification number: H01L27/0802 ,  H01L29/8605

Abstract: An integrated circuit includes a substrate and a resistor. The resistor is formed from at least two access wells of a first conductivity type and a deep buried layer electrically connecting the wells. The deep buried layer is at least partly covered by a region of opposite conductivity.

Abstract translation: 集成电路包括基板和电阻器。 电阻器由至少两个第一导电类型的访问阱和电连接阱的深埋层形成。 深埋层至少部分地被相反电导率的区域覆盖。

公开(公告)号：US07110741B2

公开(公告)日：2006-09-19

申请号：US10722245

申请日：2003-11-25

Applicant: Vincent Knopik ,  Didier Belot

Inventor： Vincent Knopik ,  Didier Belot

IPC: H04B1/28

CPC classification number: H01Q23/00 ,  H01Q9/04

Abstract: A radiofrequency unit comprising a first dielectric substrate supporting a first conductive antenna layer; a second dielectric substrate supporting circuit elements connected or coupled to ground formed in a second conductive layer, and comprising a radiofrequency antenna line; and a third screen conductive layer arranged between the first and second substrates, provided with a slot to couple the antenna line to the antenna layer, this conductive layer being floating; in which the thickness and the nature of the second substrate are chosen by taking into account the surface of said circuit elements for the screen layer to be coupled to ground by a capacitor forming a short-circuit for radiofrequencies.

Abstract translation: 一种射频单元，包括支撑第一导电天线层的第一电介质基片; 第二电介质基板，支撑连接或耦合到形成在第二导电层中的地面的电路元件，并且包括射频天线线; 以及布置在第一和第二基板之间的第三屏幕导电层，设置有用于将天线线耦合到天线层的槽，该导电层是浮动的; 其中通过考虑用于形成用于射频的短路的电容器耦合到地的屏蔽层的所述电路元件的表面来选择第二衬底的厚度和性质。

公开(公告)号：US07109609B2

公开(公告)日：2006-09-19

申请号：US10415442

申请日：2001-10-30

Applicant: Jean Jalade ,  Jean-Pierre Laur ,  Jean-Louis Sanchez ,  Patrick Austin ,  Marie Breil ,  Eric Bernier

Inventor： Jean Jalade ,  Jean-Pierre Laur ,  Jean-Louis Sanchez ,  Patrick Austin ,  Marie Breil ,  Eric Bernier

IPC: H01H83/00 ,  H02B1/24

CPC classification number: H02M1/081 ,  H02M5/2573 ,  Y10T307/826

Abstract: The invention concerns the control of thyristor-type semiconductor power components (Sw) powered by an alternating current network (VS). The control signal is a pulse (Ie). It is stored in the form of magnetic induction (B), positive or negative, in a core (T) made of ferromagnetic material. At each current alternation of the network, the interrogation of the magnetic state of the strand results in the presence, or not, of a control signal on the power device (Sw).

Abstract translation: 本发明涉及由交流网络（VS）供电的晶闸管型半导体功率元件（Sw）的控制。 控制信号是脉冲（Ie）。 它以由铁磁材料制成的铁芯（T）中的磁感应（B）的形式存储，正或负。 在网络的每个当前交替时，链的磁状态的询问导致功率设备（Sw）上的控制信号的存在或不存在。

公开(公告)号：US20060196855A1

公开(公告)日：2006-09-07

申请号：US11367672

申请日：2006-03-03

Applicant: Jean-Raphael Bezal ,  Gilles Troussel ,  Jean-Marie Permezel

Inventor： Jean-Raphael Bezal ,  Gilles Troussel ,  Jean-Marie Permezel

IPC: B23K10/00

CPC classification number: G09G3/2965

Abstract: A method and circuit to control of a circuit for addressing at least one line electrode of a plasma display panel having, for each line, a line selection stage formed of two switches in series between two input terminals of the selection stage, the method including use of a first one of the two switches of the selection stage of each line to flow a current from or to an inductive element of the addressing circuit.

Abstract translation: 一种用于控制电路的方法和电路，用于寻址等离子体显示面板的至少一个线电极，其中，对于每一行，具有由选择级的两个输入端之间串联的两个开关构成的线选择级，该方法包括使用 每行的选择级的两个开关中的第一个开关中的第一个以使来自寻址电路的电感元件的电流流向寻址电路的电感元件。

公开(公告)号：US07103015B1

公开(公告)日：2006-09-05

申请号：US09517417

申请日：2000-03-02

Applicant: Olivier Isson ,  Tomas Nordstrom

Inventor： Olivier Isson ,  Tomas Nordstrom

IPC: H04B3/20

CPC classification number: H04B3/231 ,  H04L27/2647

Abstract: A digital subscriber line transmission system comprising an IFFT circuit generating successive outgoing time domain symbols on a subscriber line from respective groups of digital frequency domain coefficients; an FFT circuit generating groups of digital frequency domain coefficients from respective incoming time domain symbols received on the subscriber line, a current incoming symbol being delayed with respect to a current outgoing symbol by a predetermined time interval; and circuitry for, during an end portion of a current incoming symbol, subtracting from the signal received on the subscriber line an estimated echo obtained by a filter from a signal portion following the end of the current outgoing symbol, and adding thereto, through said filter, a beginning portion of the current outgoing symbol, wherein said portions have a duration at least equal to said predetermined time interval.

Abstract translation: 一种数字用户线路传输系统，包括：IFFT电路，用于在来自相应的数字频域系数组的用户线路上产生连续的输出时域符号; FFT电路，生成来自在用户线路上接收的相应输入时域符号的数字频域系数组，当前输入符号相对于当前输出符号延迟预定时间间隔; 以及用于在当前输入符号的结束部分期间从在所述用户线路上接收到的信号中减去由所述当前输出符号结束之后的信号部分中由滤波器获得的估计回波，并且通过所述滤波器 ，当前输出符号的开始部分，其中所述部分具有至少等于所述预定时间间隔的持续时间。

公开(公告)号：US20060189157A1

公开(公告)日：2006-08-24

申请号：US11335857

申请日：2006-01-19

Applicant: Michel Marty ,  Gregory Avenier

Inventor： Michel Marty ,  Gregory Avenier

IPC: H01L21/31 ,  H01L21/469

CPC classification number: H01L21/76286

Abstract: An integrated circuit semiconductor substrate includes an active silicon layer separated from a silicon substrate layer by a buried insulating material layer. The active silicon layer, however, locally includes at least one over-thickness on the side of the buried layer, while maintaining a flat surface state of the semiconductor layer across the integrated circuit. The over-thickness is created by forming a cavity under the active silicon layer in the local area, and then providing the over-thickness by partially filling the cavity at the bottom of the active silicon layer through epitaxial growth. An insulating layer then fills the remaining portions of the cavity.