公开(公告)号：US20200333399A1

公开(公告)日：2020-10-22

申请号：US16387809

申请日：2019-04-18

Applicant: STMicroelectronics International N.V.

Inventor： Venkata Narayanan SRINIVASAN ,  Shiv Kumar VATS ,  HIMANSHU

IPC: G01R31/3185 ,  G01R31/3187 ,  G01R31/3183

Abstract: A test circuit includes a BIST clock generator and a functional clock generator. A first multiplexer selectively passes the BIST clock or the functional clock as a selected clock in response to a clock selection signal. BIST logic operates based upon the BIST clock. Functional logic operating based upon the functional clock signal. A memory operates based upon the selected clock. When the test circuit is operating in BIST mode, a clock selection circuit receives and passes a BIST signal as the clock selection signal. When the test circuit is operating in a shift phase of a scan test mode, it generates the clock selection signal as asserted, and when the test circuit is operating in the capture phase of the scan test mode, it generates the clock signal as equal to a last bit received from a scan chain.

公开(公告)号：US10771073B2

公开(公告)日：2020-09-08

申请号：US16696247

申请日：2019-11-26

Applicant: STMicroelectronics International N.V.

Inventor： Nitin Gupta

IPC: H03L7/099 ,  H03L7/10 ,  H03L7/087

Abstract: An oscillator circuit powered by a source voltage generates an oscillating output signal. The oscillating output signal is level shifted and applied to a first input of a multiplexer. A second input of the multiplexer receives the oscillating output signal. The multiplexer selects one of the oscillating output signal and the level shifted oscillating output signal for output as a selected oscillating output signal in response to a select signal. A locked loop circuit generates controls a frequency of the oscillating output signal as a function of the selected oscillating output signal and a reference oscillating signal. The select signal further selects one of a reference voltage and the source voltage of the oscillator circuit as an error amplifier reference voltage for a voltage regulator circuit that generates the first power supply voltage.

公开(公告)号：US10749616B2

公开(公告)日：2020-08-18

申请号：US16538490

申请日：2019-08-12

Applicant: STMicroelectronics International N.V.

Inventor： Nicolas Cordier

IPC: H04B17/21 ,  G06K7/00 ,  G06K7/10 ,  H04B5/00

Abstract: A method for a phase calibration in a frontend circuit of a near field communication (NFC) tag device is disclosed. An active load modulation signal is generated with a preconfigured value of a phase difference with respect to a reference signal of an NFC signal generator device. An amplitude of a test signal present at an antenna of the NFC tag device is measured. The test signal results from overlaying of the reference signal with the active load modulation signal. The following steps are repeated: modifying the value of the phase difference, providing the active load modulation signal with the modified value of the phase difference, measuring an amplitude of the test signal and comparing the measured amplitude with the previously measured amplitude until the measured amplitude fulfills a predefined condition. The value of the phase difference corresponding to the previously measured amplitude is stored.

公开(公告)号：US20200243153A1

公开(公告)日：2020-07-30

申请号：US16742292

申请日：2020-01-14

Applicant: STMicroelectronics International N.V.

Inventor： Shishir KUMAR ,  Abhishek PATHAK

IPC: G11C29/38 ,  G11C8/10 ,  G11C29/44

Abstract: A row decoder located on one side of a memory array selectively drives word lines in response to a row address. A word line fault detection circuit located on an opposite side of the first memory array operates to detect an open word line fault between the opposed sides of the memory array. The word line fault detection circuit includes a first clamp circuit that operates to clamp the word lines to ground. An encoder circuit encodes signals on the word lines to generate an encoded address. The encoded address is compared to the row address by a comparator circuit which sets an error flag indicating the open word line fault has been detected if the encoded address does not match the row address.

公开(公告)号：US10716186B2

公开(公告)日：2020-07-14

申请号：US16514275

申请日：2019-07-17

Applicant: STMicroelectronics International N.V.

Inventor： Akshat Jain ,  Ranajay Mallik

IPC: H05B45/37 ,  H02M3/15 ,  H02M1/08 ,  H02M3/156 ,  H05B45/10 ,  H02M1/00

Abstract: A circuit includes a voltage converter converting a source voltage to a supply voltage at a first node as a function of a feedback voltage at a feedback node. A first output path is coupled between the first node and a second node. Feedback circuitry compares the voltage at the second node to first and second overvoltages, and selectively couples the second node to the feedback node based thereupon. Impedance circuitry is coupled between the first node and a third node. A light emitting diode (LED) chain is coupled to the third node, and is selectively turned on and off as a function of the selective coupling of the second node to the feedback node by the feedback circuitry.

公开(公告)号：US20200186155A1

公开(公告)日：2020-06-11

申请号：US16696247

申请日：2019-11-26

Applicant: STMicroelectronics International N.V.

Inventor： Nitin GUPTA

IPC: H03L7/099 ,  H03L7/087 ,  H03L7/10

Abstract: An oscillator circuit powered by a source voltage generates an oscillating output signal. The oscillating output signal is level shifted and applied to a first input of a multiplexer. A second input of the multiplexer receives the oscillating output signal. The multiplexer selects one of the oscillating output signal and the level shifted oscillating output signal for output as a selected oscillating output signal in response to a select signal. A locked loop circuit generates controls a frequency of the oscillating output signal as a function of the selected oscillating output signal and a reference oscillating signal. The select signal further selects one of a reference voltage and the source voltage of the oscillator circuit as an error amplifier reference voltage for a voltage regulator circuit that generates the first power supply voltage.

公开(公告)号：US20200161031A1

公开(公告)日：2020-05-21

申请号：US16668023

申请日：2019-10-30

Applicant: STMicroelectronics International N.V.

Inventor： Mohit KAUSHIK ,  Anil KUMAR

IPC: H01C17/26 ,  H01L21/66

Abstract: A resistance trimming circuit has a resolution of N=X+Y bits. Included is a first circuit with M resistors, where M=2X−1, with each of the M resistors having a resistance of R*(2Y)*i, i being an index having a value ranging from 1 to 2X−1. M switches are associated with the M resistors. Each of the M resistors is coupled between a first node and its one of the M switches, and each of the M switches couples its one of the M resistors to a second node. Included is a second circuit with P resistors, where P=2Y−1, with each of the P resistors having a resistance of R*i. P switches are associated with the P resistors. Each of the P resistors is coupled between the second node and its one of the P switches, and each of the P switches selectively couples its one of the P resistors to a third node.

公开(公告)号：US10585143B2

公开(公告)日：2020-03-10

申请号：US16031960

申请日：2018-07-10

Applicant: STMICROELECTRONICS SA ,  STMICROELECTRONICS (CROLLES 2) SAS ,  STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Pascal Urard ,  Florian Cacho ,  Vincent Huard ,  Alok Kumar Tripathi

IPC: G01R31/3183 ,  G01R31/3185 ,  G01R31/3177 ,  G01R31/317 ,  G01R31/3181 ,  G06F17/50

Abstract: A flip flop includes a data input, a clock input, a test chain input, a test chain output, a monitoring circuit, and an alert transmission circuit. The monitoring circuit is adapted to generate an alert if the time between arrival of a data bit and a clock edge is less than a threshold. The alert transmission circuit is adapted to apply during a monitoring phase an alert level to the test chain output in the event of an alert generated by the monitoring circuit, and to apply the alert level to the test chain output when an alert level is received at the test chain input.

公开(公告)号：US10528422B2

公开(公告)日：2020-01-07

申请号：US15810731

申请日：2017-11-13

Applicant: STMicroelectronics International N.V. ,  STMicroelectronics S.r.l. ,  STMicroelectronics (Crolles 2) SAS

Inventor： Om Ranjan ,  Riccardo Gemelli ,  Denis Dutey

IPC: G06F11/10 ,  G11C29/52

Abstract: Application data and error correction code (ECC) checkbits associated with that application data are stored in a first memory. The ECC checkbits, but not the application data, are stored in a second memory. In response to a request to read the application data from the first memory, the ECC checkbits from the first memory are also read and used to detect, and possibly correct, errors in the read application data. The ECC checkbits are further output from both the first and second memories for bit-by-bit comparison. In response to a failure of the bit-by-bit comparison, a signal indicating possible malfunction of one or the other or both of the first and second memories is generated.

公开(公告)号：US10482819B2

公开(公告)日：2019-11-19

申请号：US15809007

申请日：2017-11-10

Applicant: STMicroelectronics International N.V.

Inventor： Jerome Nebon ,  Jean-Marie Permezel

IPC: G09G3/325 ,  G09G3/3225 ,  G09G3/3266 ,  G09G3/3275

Abstract: A device includes a matrix of active pixels, with each active pixel having an OLED diode having a cathode to receive a cathode voltage, and a control circuit coupled to an anode of the OLED diode. The device also includes at least one dummy pixel having a dummy OLED diode having a cathode to receive the cathode voltage, and an anode, and a dummy control circuit coupled to the anode of the OLED diode and having a power supply terminal. The dummy OLED diode and the dummy control circuit are substantially similar to the OLED diode and the control circuit. First regulation circuitry is configured to deliver a reference current to the power supply terminal to thereby generate a voltage, and second regulation circuitry is configured to regulate the cathode voltage so as to maintain the voltage at the power supply terminal at a given level.