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公开(公告)号：US10716186B2
公开(公告)日：2020-07-14
申请号：US16514275
申请日：2019-07-17
Applicant: STMicroelectronics International N.V.
Inventor： Akshat Jain , Ranajay Mallik
Abstract: A circuit includes a voltage converter converting a source voltage to a supply voltage at a first node as a function of a feedback voltage at a feedback node. A first output path is coupled between the first node and a second node. Feedback circuitry compares the voltage at the second node to first and second overvoltages, and selectively couples the second node to the feedback node based thereupon. Impedance circuitry is coupled between the first node and a third node. A light emitting diode (LED) chain is coupled to the third node, and is selectively turned on and off as a function of the selective coupling of the second node to the feedback node by the feedback circuitry.
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公开(公告)号：US20160105017A1
公开(公告)日：2016-04-14
申请号：US14509427
申请日：2014-10-08
Inventor： Ranajay Mallik , Luigi Abbatelli , Giuseppe Catalisano , Akshat Jain
CPC classification number: H02H7/205 , H02H1/0007 , H03K17/0828 , H03K17/166 , H03K17/168 , H05B6/062
Abstract: A drive transistor is connected to a resonant load in a low-side drive configuration. The voltage across the conduction terminals of the drive transistor is sensed and compared to an over-voltage threshold. An over-voltage signal is asserted in response to the comparison. The drive transistor is controlled by a PWM control signal in normal mode. In response to the assertion of the over-voltage signal, the drive transistor is forced to turn on (irrespective of the PWM control signal) to relieve the over-voltage condition. Operation of the circuit may be disabled or forced into soft start mode in response to the assertion of the over-voltage signal. Additionally, the pulse width of the PWM control signal may be reduced in response to the assertion of the over-voltage signal.
Abstract translation: 驱动晶体管以低侧驱动配置连接到谐振负载。 检测驱动晶体管的导通端子两端的电压并将其与过电压阈值进行比较。 响应于比较来断言过电压信号。 驱动晶体管由正常模式下的PWM控制信号控制。 响应于过电压信号的断言，驱动晶体管被强制导通（不管PWM控制信号如何）以减轻过电压状况。 响应于过电压信号的断言，电路的操作可能被禁用或强制进入软启动模式。 此外，可以响应于过电压信号的断言而减小PWM控制信号的脉冲宽度。
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公开(公告)号：US12107486B2
公开(公告)日：2024-10-01
申请号：US18234137
申请日：2023-08-15
Applicant: STMicroelectronics International N.V.
Inventor： Akshat Jain
IPC: H02M1/08 , H02M1/32 , H03K17/082 , H05B6/10 , H02M7/04
CPC classification number: H02M1/08 , H02M1/32 , H03K17/0828 , H05B6/108 , H02M7/04
Abstract: Methods of operating an induction geyser include drawing current through a resonant tank via a transistor, generating a changing magnetic field around the resonant tank. Owing to the strategic placement of the resonant tank in proximity to a fluid tank, the changing magnetic field envelopes the fluid tank. In a first method, the voltage across the transistor's conduction terminals is monitored, and when this voltage surpasses a predefined threshold, indicating an overvoltage condition, a corrective action is initiated in which a gate driver pulls up a gate drive signal that drives the transistor. In a second method, the current flowing between the transistor's conduction terminals is monitored, and upon detecting an overcurrent condition where the current exceeds a set threshold the gate driver is activated to pull down the gate drive signal. Both methods aim to keep operation of the geyser within desired parameters.
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4.发明授权公开(公告)号：US11855527B1
公开(公告)日：2023-12-26
申请号：US17834174
申请日：2022-06-07
Applicant: STMicroelectronics International N.V.
Inventor： Ranajay Mallik , Akshat Jain
CPC classification number: H02M1/4216 , H02M1/12 , H02M1/4225 , H02M1/4233 , H02M7/2173 , H02M7/2176 , H02M1/42 , H02M7/217
Abstract: A PFC correction circuit includes first, second, and third phase inputs coupled to three-phase power mains, with a three-phase full-wave rectifying bridge connected to an input node. First, second, and third boost inductors are respectively connected between first, second, and third phase inputs and first, second, and third taps of the three-phase full-wave rectifying bridge. A boost switch is connected between the input node and ground, and a boost diode is connected between the input node and an output node. A multiplier input driver generates a single-phase input signal as a replica of a signal at the three-phase power mains after rectification. A single-phase power factor controller generates a PWM signal from the single-phase input signal. A gate driver generates a gate drive signal from the PWM signal. The boost switch is operated by the gate drive signal.
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公开(公告)号：US10897192B1
公开(公告)日：2021-01-19
申请号：US16671318
申请日：2019-11-01
Applicant: STMicroelectronics International N.V.
Inventor： Akshat Jain , Saurabh Sona
IPC: H02M1/10 , H02M1/36 , H03K17/615 , H02M1/00
Abstract: A Darlington switch in series with a biasing circuit is biased in an ON state by default to generate a supply voltage for a controller integrated circuit chip during start-up. On powering up, the supply voltage for the controller integrated circuit chip rises. When the supply voltage exceeds a minimum operating voltage threshold, the controller integrated circuit chip is enabled for operation and an auxiliary supply circuit begins generating the supply voltage for the controller integrated circuit chip. The Darlington switch is turned OFF when the supply voltage being generated by the auxiliary circuit is sufficiently higher than a threshold associated with the minimum operating voltage threshold. The circuit for controlling ON/OFF state of the Darlington switch has a substantially lower static power dissipation than the biasing circuit.
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Patent Agency Ranking
公开(公告)号：US10302695B2
公开(公告)日：2019-05-28
申请号：US15797504
申请日：2017-10-30
Applicant: STMICROELECTRONICS INTERNATIONAL N.V.
Inventor： Tejinder Kumar , Akshat Jain
IPC: G01R31/317 , G01R31/3177
Abstract: Various embodiments provide a parallel checker to determine whether a device under test (DUT) is functioning properly or outputting erroneous bits. A test pattern or test data is injected into the DUT, and the parallel checker compares output data of the DUT to expected data stored in the parallel checker. The parallel checker determines an error in the event that a bit in the output data does not match in the expected data. The parallel checker is independent of test pattern length and data width at the parallel input of the parallel checker. Accordingly, the parallel checker may be used for multiple different test patterns, such as a PRBS 7, a CJTPAT, CRPAT, etc. Further, the parallel checker provides high-speed synchronization between data received from the DUT and expected test data stored in the parallel checker. In addition, the parallel checker consumes relatively low power and chip area in, for example, a SoC environment.
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公开(公告)号：US09331474B1
公开(公告)日：2016-05-03
申请号：US14509427
申请日：2014-10-08
Inventor： Ranajay Mallik , Luigi Abbatelli , Giuseppe Catalisano , Akshat Jain
CPC classification number: H02H7/205 , H02H1/0007 , H03K17/0828 , H03K17/166 , H03K17/168 , H05B6/062
Abstract: A drive transistor is connected to a resonant load in a low-side drive configuration. The voltage across the conduction terminals of the drive transistor is sensed and compared to an over-voltage threshold. An over-voltage signal is asserted in response to the comparison. The drive transistor is controlled by a PWM control signal in normal mode. In response to the assertion of the over-voltage signal, the drive transistor is forced to turn on (irrespective of the PWM control signal) to relieve the over-voltage condition. Operation of the circuit may be disabled or forced into soft start mode in response to the assertion of the over-voltage signal. Additionally, the pulse width of the PWM control signal may be reduced in response to the assertion of the over-voltage signal.
Abstract translation: 驱动晶体管以低侧驱动配置连接到谐振负载。 检测驱动晶体管的导通端子两端的电压并将其与过电压阈值进行比较。 响应于比较来断言过电压信号。 驱动晶体管由正常模式下的PWM控制信号控制。 响应于过电压信号的断言，驱动晶体管被强制导通（不管PWM控制信号如何）以减轻过电压状况。 响应于过电压信号的断言，电路的操作可能被禁用或强制进入软启动模式。 此外，可以响应于过电压信号的断言而减小PWM控制信号的脉冲宽度。
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公开(公告)号：US11764662B2
公开(公告)日：2023-09-19
申请号：US16984756
申请日：2020-08-04
Applicant: STMicroelectronics International N.V.
Inventor： Akshat Jain
CPC classification number: H02M1/08 , H02M1/32 , H03K17/0828 , H05B6/108 , H02M7/04
Abstract: A circuit includes a transistor, with a resonant tank coupled between a DC supply node and a first conduction terminal of the transistor. A gate driver generates a gate drive signal for biasing a control terminal of the transistor to cause it to conduct current through the resonant tank. Control circuitry monitors a voltage across the transistor to determine that the transistor is an overvoltage condition if that voltage exceeds a threshold, and monitors a current through the transistor to determine that the transistor is an overcurrent condition if that current exceeds a threshold. If overvoltage is determined, the control circuitry causes the gate driver to pull up the gate drive signal. If overcurrent is determined, the control circuitry causes the gate driver to pull down the gate drive signal. If either overvoltage or overcurrent is present, a pulse width of the gate drive signal is reduced.
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公开(公告)号：US11621645B2
公开(公告)日：2023-04-04
申请号：US16892385
申请日：2020-06-04
Inventor： Akshat Jain , Ivan Clemente Massimiani
Abstract: A driving circuit including a reference voltage generator to generate a reference voltage based on an operating frequency of a complementary circuit; a comparator including a first input configured to receive a drain-to-source voltage of a field effect transistor; and a second input to receive the reference voltage; and a signal generator to deliver a driving signal to a gate terminal of the field effect transistor to drive the field effect transistor to an ON state after the drain-to-source voltage of the first low side field effect transistor becomes less than the reference voltage and to an OFF state after the drain-to-source voltage of the field effect transistor becomes greater than the reference voltage.
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公开(公告)号：US11296591B2
公开(公告)日：2022-04-05
申请号：US17121374
申请日：2020-12-14
Applicant: STMicroelectronics International N.V.
Inventor： Akshat Jain
IPC: H05B45/18 , H05B45/355 , H02M1/08 , H02M1/42 , H05B45/44 , H05B45/375 , H02M1/00
Abstract: A LED driving circuit includes a power factor correction circuit receiving a rectified mains voltage and providing output to a DC voltage bus, a string of LEDs connected in series, a voltage converter receiving input from the DC voltage bus and providing output to the string of LEDs, and a microcontroller. The microcontroller receives a plurality of digital feedback signals from the voltage converter, controls the voltage converter based upon a user desired brightness level and the plurality of digital feedback signals, and receive a plurality of feedback signals from the power factor correction circuit. Based on the plurality of feedback signals, the microcontroller operates the power factor correction circuit in transition mode where the user desired brightness level is above a threshold brightness, and operates the power factor correction circuit in discontinuous mode where the user desired brightness level is below the threshold brightness.
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