公开(公告)号：US11029715B1

公开(公告)日：2021-06-08

申请号：US16853644

申请日：2020-04-20

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  John Eric Linstadt

IPC: G05F1/567 ,  G05F1/56

Abstract: A voltage converter includes first and second inputs to receive a supply voltage and a reference voltage, respectively, from a power supply component, the supply voltage being higher than the reference voltage by a scaling factor of at least five. The voltage converter iteratively charges an internal filter capacitor to produce a converted voltage that follows the reference voltage by switchably coupling the first input to the filter capacitor while the converted voltage is less than the reference voltage to raise the converted voltage, and by switchably decoupling the first input from the filter capacitor while the converted voltage exceeds the reference voltage to enable the converted voltage to decay.

公开(公告)号：US11018907B2

公开(公告)日：2021-05-25

申请号：US16899513

申请日：2020-06-11

Applicant: Rambus Inc.

Inventor： Nanyan Wang

IPC: H03K7/02 ,  H03K9/02 ,  H04L25/06 ,  H04L5/00 ,  H04L25/49 ,  H04L27/00

Abstract: In a PAM-N receiver, sampler reference levels, DC offset and AFE gain may be jointly adapted to achieve optimal or near-optimal boundaries for the symbol decisions of the PAM-N signal. For reference level adaptation, the hamming distances between two consecutive data samples and their in-between edge sample are evaluated. Reference levels for symbol decisions are adjusted accordingly such that on a data transition, an edge sample has on average, equal hamming distance to its adjacent data samples. DC offset may be compensated to ensure detectable data transitions for reference level adaptation. AFE gains may be jointly adapted with sampler reference levels such that the difference between a reference level and a pre-determined target voltage is minimized.

公开(公告)号：US20210152402A1

公开(公告)日：2021-05-20

申请号：US17110530

申请日：2020-12-03

Applicant: Rambus Inc.

Inventor： Hae-Chang Lee ,  Brian S. Leibowitz ,  Jade M. Kizer ,  Thomas H. Greer ,  Akash Bansal

IPC: H04L25/03 ,  H04B1/12

Abstract: A receiver includes a continuous-time equalizer, a decision-feedback equalizer (DFE), data and error sampling logic, and an adaptation engine. The receiver corrects for inter-symbol interference (ISI) associated with the most recent data symbol (first post cursor ISI) by establishing appropriate equalization settings for the continuous-time equalizer based upon a measure of the first-post-cursor ISI.

公开(公告)号：US11003601B2

公开(公告)日：2021-05-11

申请号：US16837844

申请日：2020-04-01

Applicant: Rambus Inc.

Inventor： Chi-Ming Yeung ,  Yoshie Nakabayashi ,  Thomas Giovannini ,  Henry Stracovsky

IPC: G06F13/20 ,  G06F13/16 ,  G06F13/40 ,  G06F13/42

Abstract: A mother board topology including a processor operable to be coupled to one or more communication channels for communicating commands. The topology includes a first communication channel electrically coupling a first set of two or more dual in-line memory modules (DIMMs) and a first primary data buffer on a mother board. The topology includes a second communication channel electrically coupling a second set of two or more DIMMs and a second primary data buffer on the mother board. The topology includes a third channel electrically coupling the first primary data buffer, the primary second data buffer, and the processor.

公开(公告)号：US20210134347A1

公开(公告)日：2021-05-06

申请号：US16953196

申请日：2020-11-19

Applicant: Rambus Inc.

Inventor： Jade M. Kizer ,  Sivakumar Doraiswamy ,  Benedict Lau

IPC: G11C11/4076 ,  G06F13/16 ,  G06F13/40 ,  G11C8/18 ,  G11C7/22 ,  G11C11/4063 ,  G11C11/4072 ,  G11C11/4096

Abstract: An integrated circuit (IC) memory controller is disclosed. The memory controller includes a receiver to receive a strobe signal and provide an internal strobe signal. An adjustable delay circuit delays an enable signal to generate a delayed enable signal. A gate circuit generates a gated strobe signal using the delayed enable signal that masks transitions of the internal strobe signal that occur prior to a valid region of the internal strobe signal. A sample circuit samples data using the gated strobe signal.

公开(公告)号：US20210105016A1

公开(公告)日：2021-04-08

申请号：US17082467

申请日：2020-10-28

Applicant: Rambus Inc.

Inventor： Marcus VAN IERSSEL ,  Dominic DICLEMENTE

IPC: H03M1/06 ,  H03M7/16

Abstract: A phase rotator receives control signals and thermometer coded signals that specifies the phase of an output signal. The phase rotator may be used, for example, by a clock and data recovery (CDR) circuit to continually rotate the phase of a clock to compensate for phase/frequency mismatches between received data and the clock. The control signals determine the phase quadrant (i.e., 0°-90°, 90°-180°, etc.) of the output signal. The thermometer coded signals determine the phase of the output signal within a quadrant by steering a set of bias currents between two or more nodes. The set of bias currents are selected to reduce the non-linearity between the thermometer coded value and the phase of the output signal.

公开(公告)号：US20210098033A1

公开(公告)日：2021-04-01

申请号：US17065278

申请日：2020-10-07

Applicant: Rambus Inc.

Inventor： James E. Harris ,  Thomas Vogelsang ,  Frederick A. Ware ,  Ian P. Shaeffer

IPC: G11C7/10 ,  G11C7/08 ,  G11C5/02 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4091 ,  G11C7/06 ,  G11C7/12 ,  G11C7/22 ,  G11C8/08 ,  G11C8/10

Abstract: Row activation operations within a memory component are carried out with respect to subrows instead of complete storage rows to reduce power consumption. Further, instead of activating subrows in response to row commands, subrow activation operations are deferred until receipt of column commands that specify the column operation to be performed and the subrow to be activated.

公开(公告)号：US20210090614A1

公开(公告)日：2021-03-25

申请号：US17068505

申请日：2020-10-12

Applicant: Rambus Inc.

Inventor： Scott C. BEST ,  John W. POULTON

IPC: G11C5/14 ,  H04L25/02 ,  G06F13/40 ,  H04L1/20 ,  H04L25/08 ,  G06F11/07

Abstract: In a data transmission system, one or more signal supply voltages for generating the signaling voltage of a signal to be transmitted are generated in a first circuit and forwarded from the first circuit to a second circuit. The second circuit may use the forwarded signal supply voltages to generate another signal to be transmitted back from the second circuit to the first circuit, thereby obviating the need to generate signal supply voltages separately in the second circuit. The first circuit may also adjust the signal supply voltages based on the signal transmitted back from the second circuit to the first circuit. The data transmission system may employ a single-ended signaling system in which the signaling voltage is referenced to a reference voltage that is a power supply voltage such as ground, shared by the first circuit and the second circuit.

公开(公告)号：US20210089464A1

公开(公告)日：2021-03-25

申请号：US17064342

申请日：2020-10-06

Applicant: Rambus Inc.

Inventor： Frederick A. Ware

IPC: G06F12/0895 ,  G06F12/0846 ,  G11C8/06 ,  G06F12/1027 ,  G06F12/0802

Abstract: A memory controller includes logic circuitry to generate a first data address identifying a location in a first external memory array for storing first data, a first tag address identifying a location in a second external memory array for storing a first tag, a second data address identifying a location in the second external memory array for storing second data, and a second tag address identifying a location in the first external memory array for storing a second tag. The memory controller includes an interface that transfers the first data address and the first tag address for a first set of memory operations in the first and the second external memory arrays. The interface transfers the second data address and the second tag address for a second set of memory operations in the first and the second external memory arrays.

公开(公告)号：US20210044417A1

公开(公告)日：2021-02-11

申请号：US17000182

申请日：2020-08-21

Applicant: Rambus Inc.

Inventor： Bret G. Stott ,  Craig E. Hampel ,  Frederick A. Ware

IPC: H04L7/033 ,  H04L7/00 ,  G11C7/10 ,  G11C7/20 ,  G11C7/22 ,  H03L7/081 ,  H04L1/20

Abstract: A signaling system is disclosed. The signaling system includes a first integrated circuit (IC) chip to receive a data signal and a strobe signal. The first IC includes circuitry to sample the data signal at times indicated by the strobe signal to generate phase error information and circuitry to output the phase error information from the first IC device. The system further includes a signaling link and a second IC chip coupled to the first IC chip via the signaling link to output the data signal and the strobe signal to the first IC chip. The second IC chip includes delay circuitry to generate the strobe signal by delaying an aperiodic timing signal for a first time interval and timing control circuitry to receive the phase error information from the first IC chip and adjust the first time interval in accordance with the phase error information.