公开(公告)号：US20220271165A1

公开(公告)日：2022-08-25

申请号：US17663267

申请日：2022-05-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd

Inventor： Kuo-Cheng Chiang ,  Chi-Wen Liu ,  Ying-Keung Leung

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/423 ,  H01L29/786 ,  H01L29/775 ,  B82Y10/00 ,  H01L29/06

Abstract: A device includes a first semiconductor strip, a first gate dielectric encircling the first semiconductor strip, a second semiconductor strip overlapping the first semiconductor strip, and a second gate dielectric encircling the second semiconductor strip. The first gate dielectric contacts the first gate dielectric. A gate electrode has a portion over the second semiconductor strip, and additional portions on opposite sides of the first and the second semiconductor strips and the first and the second gate dielectrics.

公开(公告)号：US11424242B2

公开(公告)日：2022-08-23

申请号：US16871740

申请日：2020-05-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shi-Ning Ju ,  Kuo-Cheng Chiang ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC: H01L27/088 ,  H01L29/423 ,  H01L29/786 ,  H01L29/78 ,  H01L29/66 ,  H01L21/762 ,  H01L29/08 ,  H01L21/8234

Abstract: A semiconductor device structure and a method for forming a semiconductor device structure are provided. The semiconductor device structure includes a semiconductor fin over a substrate and multiple semiconductor nanostructures suspended over the semiconductor fin. The semiconductor device structure also includes a gate stack extending across the semiconductor fin, and the gate stack wraps around each of the semiconductor nanostructures. The semiconductor device structure further includes a first epitaxial structure and a second epitaxial structure sandwiching the semiconductor nanostructures. Each of the first epitaxial structure and the second epitaxial structure extends exceeding a top surface of the semiconductor fin. In addition, the semiconductor device structure includes an isolation structure between the semiconductor fin and the gate stack. The isolation structure further extends exceeding opposite sidewalls of the first epitaxial structure.

公开(公告)号：US20220181259A1

公开(公告)日：2022-06-09

申请号：US17682701

申请日：2022-02-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Cheng Chiang ,  Shi Ning Ju ,  Chih-Chao Chou ,  Wen-Ting Lan ,  Chih-Hao Wang

IPC: H01L23/528 ,  H01L29/786 ,  H01L21/02 ,  H01L21/285 ,  H01L21/306 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/45 ,  H01L29/66

Abstract: Nanostructure field-effect transistors (nano-FETs) including isolation layers formed between epitaxial source/drain regions and semiconductor substrates and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a power rail, a dielectric layer over the power rail, a first channel region over the dielectric layer, a second channel region over the first channel region, a gate stack over the first channel region and the second channel region, where the gate stack is further disposed between the first channel region and the second channel region and a first source/drain region adjacent the gate stack and electrically connected to the power rail.

公开(公告)号：US11342325B2

公开(公告)日：2022-05-24

申请号：US16823581

申请日：2020-03-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Chao Chou ,  Chih-Hao Wang ,  Shi Ning Ju ,  Kuo-Cheng Chiang ,  Wen-Ting Lan

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/06 ,  H01L29/423

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip (IC) including a first fin structure and a second fin structure vertically extending from a semiconductor substrate, respectively. The first fin structure laterally extends along a first direction and has a first width. The second fin structure laterally extends along the first direction and has a second width that is less than the first width. A first plurality of nanostructures directly overlies the first fin structure and is vertically spaced from the first fin structure by a non-zero distance. A gate electrode continuously laterally extends along a second direction that is substantially perpendicular to the first direction. The gate electrode directly overlies the first and second fin structures, and wraps around the nanostructures.

公开(公告)号：US11296199B2

公开(公告)日：2022-04-05

申请号：US16871993

申请日：2020-05-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shi Ning Ju ,  Guan-Lin Chen ,  Kuo-Cheng Chiang ,  Chih-Hao Wang

IPC: H01L29/417 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/78

Abstract: Semiconductor devices and their manufacturing methods are disclosed herein, and more particularly to semiconductor devices including a transistor having gate all around (GAA) transistor structures and manufacturing methods thereof. The methods described herein allow for complex shapes (e.g., “L-shaped”) to be etched into a multi-layered stack to form fins used in the formation of active regions of the GAA nanostructure transistor structures. In some embodiments, the active regions may be formed with a first channel width and a first source/drain region having a first width and a second channel width and a second source/drain region having a second width that is less than the first width.

公开(公告)号：US11245028B2

公开(公告)日：2022-02-08

申请号：US16776540

申请日：2020-01-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jia-Chuan You ,  Chih-Hao Wang ,  Shi Ning Ju ,  Kuo-Cheng Chiang ,  Li-Yang Chuang

IPC: H01L29/66 ,  H01L27/088 ,  H01L29/165 ,  H01L29/06

Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, a first vertical structure and a second vertical structure formed over the substrate, and an isolation structure between the first and second vertical structures. The isolation structure can include a center region and footing regions formed on opposite sides of the center region. Each of the footing regions can be tapered towards the center region from a first end of the each footing region to a second end of the each footing region.

公开(公告)号：US20220037509A1

公开(公告)日：2022-02-03

申请号：US16941504

申请日：2020-07-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jui-Chien Huang ,  Kuo-Cheng Chiang ,  Chih-Hao Wang ,  Shi Ning Ju ,  Guan-Lin Chen

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/78 ,  H01L29/423

Abstract: A device includes a first channel layer over a semiconductor substrate, a second channel layer over the first channel layer, and a third channel layer over the second channel layer. The channel layers each connects a first and a second source/drain along a first direction. The device also includes a first gate portion between the first and second channel layers; a second gate portion between the second and third channel layers; a first inner spacer between the first and second channel layers and between the first gate portion and the first source/drain; and a second inner spacer between the second and third channel layers and between the second gate portion and the first source/drain. The first and second gate portions have substantially the same gate lengths along the first direction. The first inner spacer has a width along the first direction that is greater than the second inner spacer has.

公开(公告)号：US20220029023A1

公开(公告)日：2022-01-27

申请号：US16935000

申请日：2020-07-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Cheng Chen ,  Kuo-Cheng Chiang ,  Zhi-Chang Lin

IPC: H01L29/786 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/66

Abstract: A semiconductor device according to the present disclosure includes an active region including a channel region and a source/drain region adjacent the channel region, a vertical stack of channel members over the channel region, a gate structure over and around the vertical stack of channel members, a bottom dielectric feature over the source/drain region, a source/drain feature over the bottom dielectric feature, and a germanium layer disposed between the bottom dielectric feature and the source/drain region.

公开(公告)号：US11211472B2

公开(公告)日：2021-12-28

申请号：US16799650

申请日：2020-02-24

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Pei-Hsun Wang ,  Shih-Cheng Chen ,  Kuo-Cheng Chiang ,  Chih-Hao Wang

IPC: H01L29/66 ,  H01L21/8234 ,  H01L27/088 ,  H01L27/092 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78

Abstract: A semiconductor device includes a semiconductor substrate having a fin structure, a gate stack across the fin structure, a spacer structure on a sidewall of the gate stack, an epitaxial structure on the semiconductor substrate, and a dielectric structure in the spacer structure. The dielectric structure extends along a lower portion of the spacer structure and across the fin structure.

公开(公告)号：US11211381B2

公开(公告)日：2021-12-28

申请号：US16910574

申请日：2020-06-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Cheng Chiang ,  Shi-Ning Ju ,  Chih-Hao Wang ,  Kuan-Ting Pan ,  Zhi-Chang Lin

IPC: H01L27/088 ,  H01L29/423 ,  H01L29/786 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/78

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes an isolation structure formed over a substrate, and a first stacked structure and a second stacked structure extending above the isolation structure. The first stacked structure includes a plurality of first nanostructures stacked in a vertical direction, and the second stacked structure includes a plurality of second nanostructures stacked in the vertical direction. The semiconductor device structure also includes a first dummy fin structure formed over the isolation structure, and the first dummy fin structure is between the first fin structure and the second fin structure. The semiconductor device structure includes a capping layer formed over the first dummy fin structure, and a top surface of the capping layer is higher than a top surface of the first stacked structure and a top surface of the second stacked structure.