公开(公告)号：US10146433B2

公开(公告)日：2018-12-04

申请号：US14812597

申请日：2015-07-29

Applicant: NOVATEK MICROELECTRONICS CORP.

Inventor： Chia-Hung Hsin

IPC: G06F15/177 ,  G06F3/06 ,  G06F9/4401

Abstract: A method for initializing a NAND flash serving as a booting device includes the following steps. A NAND flash storing a boot table being identified by an identification (ID) of the NAND flash is provided. A current block of the NAND flash is searched to read the boot table. Configuration information of the boot table is read to initialize the NAND flash.

公开(公告)号：US10146369B2

公开(公告)日：2018-12-04

申请号：US15712148

申请日：2017-09-22

Applicant: Novatek Microelectronics Corp.

Inventor： Hui-Hung Chang ,  Meng-Hsiu Wu

IPC: G06F3/041 ,  G06F13/36 ,  G06F3/044 ,  G06F8/71

Abstract: An electronic apparatus with a touch panel including a host controller, an interface unit, and a touch panel control unit is provided. The host controller is used to control an electronic apparatus implemented with the host controller. The touch panel control unit is coupled to the host controller through the interface unit. The host controller transmits an updating information to the touch panel control unit with a format of the interface unit, in which the updating data is used to update the touch panel control unit. The touch panel control unit decodes the updating data to accordingly update.

公开(公告)号：US20180330523A1

公开(公告)日：2018-11-15

申请号：US15591121

申请日：2017-05-10

Applicant: Novatek Microelectronics Corp.

Inventor： Lei Zhang ,  Yuan-Jia Du ,  Heng-Yao Lin

IPC: G06T11/00

CPC classification number: G06T11/001 ,  G09G5/02

Abstract: An image processing apparatus including an image processing circuit is provided. The image processing circuit is configured to perform a subpixel conversion operation on an input image of a first format to convert the input image of the first format to the input image of a second format; obtain a first detection result with respect to a target pixel of the input image of the first format; determine a filter parameter with respect to the target pixel according to the first detection result; and perform a subpixel rendering operation on the input image of the second format according to the determined filter parameter to obtain an output image.

公开(公告)号：US10121777B2

公开(公告)日：2018-11-06

申请号：US15275492

申请日：2016-09-26

Applicant: Novatek Microelectronics Corp.

Inventor： Chun-Yu Lin ,  Jie-Ting Chen ,  Ming-Dou Ker ,  Tzu-Chien Tzeng ,  Keko-Chun Liang ,  Ju-Lin Huang

IPC: H01L29/74 ,  H01L27/02 ,  H01L29/87 ,  H01L29/06

Abstract: A silicon controlled rectifier including a semiconductor substrate, first and second semiconductor wells, first and second semiconductor regions, third and fourth semiconductor regions and a silicide layer is provided. The first and the second semiconductor wells are formed in the semiconductor substrate. The first and the second semiconductor regions are respectively formed in the first and the second semiconductor wells in spaced apart relation. The third and the fourth semiconductor regions are respectively formed in the first and the second semiconductor wells. The silicide layer is formed on the third and the fourth semiconductor regions. The silicon controlled rectifier is at least suitable for high frequency circuit application. The silicon controlled rectifier has a relatively low trigger voltage, a relatively high electrostatic discharge level, and a relatively low capacitance.

公开(公告)号：US10110928B2

公开(公告)日：2018-10-23

申请号：US14583066

申请日：2014-12-24

Applicant: Novatek Microelectronics Corp.

Inventor： Yu-Wei Chang ,  Po-Chin Hu

IPC: H04N19/85 ,  H04N19/88 ,  H04N19/423

Abstract: A video processing apparatus and a video processing circuit of the video processing apparatus are provided. The video processing circuit includes a video processor, a first memory controller, a second memory controller and a distributor. The video processor includes at least one sub-processing-tasks processor which is configured to execute one or more sub-processing tasks respectively. The first memory controller controls a first memory. The second memory controller controls a second memory. The distributor stores the data outputted by the video processor to the first memory and the second memory through the first memory controller and the second memory controller respectively.

公开(公告)号：US20180302073A1

公开(公告)日：2018-10-18

申请号：US15488545

申请日：2017-04-17

Applicant: NOVATEK MICROELECTRONICS CORP.

Inventor： Po-Yao Ko ,  Yi-Ming Wu

IPC: H03K5/156 ,  H03K5/05 ,  H03K5/00

Abstract: A duty cycle calibration circuit and a frequency synthesizer using the same are provided. The duty cycle calibration circuit includes a single-ended correction circuit and a single-ended detection circuit. The single-ended correction circuit is configured to adjust a duty cycle of an input clock signal. The single-ended correction circuit includes a first slew rate controller, a second slew rate controller, and at least one logic gate. The first slew rate controller adjusts a rising slew rate of an output clock signal in response to a control signal. The second slew rate controller adjusts a falling slew rate of the output clock signal in response to the control signal. The single-ended detection circuit is configured to detect a duty cycle of the output clock signal by converting the duty cycle of the output clock signal to an average voltage to be served as the control signal.

公开(公告)号：US20180293926A1

公开(公告)日：2018-10-11

申请号：US16010242

申请日：2018-06-15

Applicant: NOVATEK MICROELECTRONICS CORP.

Inventor： Yu-Kuang CHANG ,  Kuei-Chung CHANG ,  Ming-Da CHIANG

IPC: G09G3/20

Abstract: A display driving circuit comprising a video signal transformation circuit, a reference voltage generating circuit, a DAC and an interpolation operational amplifier is provided. The video signal transformation circuit transforms an input video signal into a transformed video signal with a higher bit depth. The transformed video signal comprises an upper n bits data and a lower m bits data, wherein n+m equals a bit depth of the transformed video signal. The reference voltage generating circuit generates reference voltages. The DAC selects a first reference voltage and a second reference voltage to interpolation operational amplifier from the reference voltages according to an upper n bits data of the transformed video signal. The interpolation operational amplifier outputs a driving voltage to display device according to the first reference voltage, the second reference voltage and the lower m bits data of the transformed video signal.

公开(公告)号：US20180261524A1

公开(公告)日：2018-09-13

申请号：US15903044

申请日：2018-02-23

Applicant: Novatek Microelectronics Corp.

Inventor： Wen-Ching Huang ,  Chien-Chen Ko

IPC: H01L23/373 ,  B32B37/12 ,  B32B37/14 ,  B32B7/12 ,  B32B9/00 ,  H01L21/48 ,  H01L23/367 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498

CPC classification number: H01L23/373 ,  B32B7/12 ,  B32B9/007 ,  B32B37/12 ,  B32B37/14 ,  B32B2457/00 ,  H01L21/481 ,  H01L23/3142 ,  H01L23/315 ,  H01L23/367 ,  H01L23/49838 ,  H01L24/32 ,  H01L24/83 ,  H01L2224/32225

Abstract: A chip on film package includes a base film, a patterned circuit layer, a solder resist layer, a chip and a graphite sheet. The base film includes a first surface and a mounting region located on the first surface. The patterned circuit layer is disposed on the first surface. The solder resist layer partially covers the patterned circuit layer. The chip is disposed on the mounting region and electrically connected to the patterned circuit layer. The graphite sheet covers at least a part of the solder resist layer, wherein an outer edge of the graphite sheet is substantially aligned with an outer edge of the solder resist layer.

公开(公告)号：US20180261523A1

公开(公告)日：2018-09-13

申请号：US15613275

申请日：2017-06-05

Applicant: Novatek Microelectronics Corp.

Inventor： Wen-Ching Huang ,  Chien-Chen Ko

IPC: H01L23/373 ,  H01L23/498 ,  H01L23/31 ,  H01L23/00 ,  H01L23/367 ,  H01L21/48 ,  B32B9/00 ,  B32B7/12 ,  B32B37/14 ,  B32B37/12

Abstract: A chip on film package includes a base film, a patterned circuit layer, a solder resist layer, a chip and a graphite sheet. The base film includes a first surface and a mounting region located on the first surface. The patterned circuit layer is disposed on the first surface. The solder resist layer partially covers the patterned circuit layer. The chip is disposed on the mounting region and electrically connected to the patterned circuit layer. The graphite sheet covers at least a part of the solder resist layer, wherein an outer edge of the graphite sheet is substantially aligned with an outer edge of the solder resist layer.

公开(公告)号：US10074298B2

公开(公告)日：2018-09-11

申请号：US15408426

申请日：2017-01-18

Applicant: Novatek Microelectronics Corp.

Inventor： Hsueh-Yen Yang ,  Hua-Gang Chang ,  Chun-Chieh Lin

IPC: G09G3/30 ,  G09G3/20

CPC classification number: G09G5/10 ,  G06F1/1652 ,  G06F1/1677 ,  G06T5/002 ,  G06T2207/20024 ,  G09G3/2003 ,  G09G3/3208 ,  G09G2320/045 ,  G09G2320/046 ,  G09G2320/048 ,  G09G2320/0666 ,  G09G2320/103 ,  G09G2360/16 ,  G09G2380/02

Abstract: An image processing method and a display device thereof are provided. The method is adapted to a display panel with a display area. The image processing method includes the following steps. Whether original images to be displayed on a plurality of sub-areas of the display area are still is analyzed and determined. When the original image in a current sub-area is still, a time length of the original image being still is recorded. The current sub-area is one of the sub-areas. Processing levels corresponding to a plurality of image processing schemes are determined based on the time length. Overall or partial luminance (luma) of the original image in the current sub-area is gradually reduced by the image processing schemes with the determined processing levels, and a corresponding luma-reduced image is displayed on the current sub-area.