公开(公告)号：US06660578B1

公开(公告)日：2003-12-09

申请号：US10118274

申请日：2002-04-08

Applicant: Olov Karlsson ,  Qi Xiang ,  HaiHong Wang ,  Bin Yu ,  Zoran Krivokapic

Inventor： Olov Karlsson ,  Qi Xiang ,  HaiHong Wang ,  Bin Yu ,  Zoran Krivokapic

IPC: H01L218238

CPC classification number: H01L27/1203 ,  H01L21/84

Abstract: A semiconductor device, a semiconductor wafer and a method of forming a semiconductor wafer where a barrier layer is used to inhibit P-type ion-penetration into a dielectric layer made from a high-K material.

Abstract translation: 半导体器件，半导体晶片和形成半导体晶片的方法，其中阻挡层用于抑制由高K材料制成的电介质层中的P型离子渗透。

公开(公告)号：US06646307B1

公开(公告)日：2003-11-11

申请号：US10081362

申请日：2002-02-21

Applicant: Bin Yu ,  Eric N. Paton

Inventor： Bin Yu ,  Eric N. Paton

IPC: H01L2701

CPC classification number: H01L29/6675 ,  H01L29/78618 ,  H01L29/78648

Abstract: A double gate MOSFET. The MOSFET includes a bottom gate electrode and a bottom gate dielectric disposed over the bottom gate electrode. A semiconductor body region is disposed over the bottom gate dielectric and the bottom gate electrode, and disposed between a source and a drain. A top gate electrode is disposed over the body. A top gate dielectric separates the top gate electrode and the body, the top gate electrode and the bottom gate electrode defining a channel within the body and interposed between the source and the drain. At least one of the bottom gate dielectric or the top gate dielectric is formed from a high-K material. A method of forming a double gate MOSFET is also disclosed where a semiconductor film used to form a body is recrystallized using a semiconductor substrate as a seed crystal.

Abstract translation: 双栅极MOSFET。 MOSFET包括设置在底栅电极上的底栅电极和底栅电介质。 半导体本体区域设置在底栅电介质和底栅电极之上，并且设置在源极和漏极之间。 顶栅电极设置在身体上。 顶栅电介质分离顶栅电极和主体，顶栅电极和底栅电极在主体内限定通道并置于源极和漏极之间。 底栅电介质或顶栅电介质中的至少一个由高K材料形成。 还公开了一种形成双栅极MOSFET的方法，其中用于形成本体的半导体膜使用半导体衬底作为晶种再结晶。

公开(公告)号：US06630712B2

公开(公告)日：2003-10-07

申请号：US09372705

申请日：1999-08-11

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L2976

CPC classification number: H01L29/4983 ,  H01L21/28114 ,  H01L21/28167 ,  H01L21/28194 ,  H01L21/28202 ,  H01L29/42376 ,  H01L29/512 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66643 ,  H01L29/7833

Abstract: A method of fabricating an integrated circuit with a transistor having less susceptibility to off-state leakage current and short-channel effect is disclosed. The transistor includes high-K gate dielectric spacers and a T-shaped gate conductor. The high-K dielectric spacers can be tantalum pentaoxide or titanium dioxide. The process can be utilized for P-channel or N-channel metal oxide field semiconductor effect transistors (MOSFETs). The T-shaped conductor forms dynamic source/drain extensions.

Abstract translation: 公开了一种制造具有对截止状态漏电流和短沟道效应的敏感性较小的晶体管的集成电路的方法。 晶体管包括高K栅极电介质隔离物和T形栅极导体。 高K电介质隔离物可以是五氧化钽或二氧化钛。 该过程可用于P沟道或N沟道金属氧化物半导体效应晶体管（MOSFET）。 T形导体形成动态源/漏扩展。

公开(公告)号：US06630385B1

公开(公告)日：2003-10-07

申请号：US09844773

申请日：2001-04-27

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L21336

CPC classification number: H01L29/1083 ,  H01L21/26506 ,  H01L21/26586 ,  H01L29/665

Abstract: A method for improving the channel doping profile of deep-submicron field effect transistors and MOSFETs. The method involves dual halo implants annealed at different temperatures to improve the threshold voltage roll-off characteristics of MOSFETs of approximately 50 nm or less. The method includes a deep source/drain implant and anneal, followed by an angled deep halo implant and a second anneal at a lower temperature. An amorphization implant is then made, followed by a second angled halo implant, formation of source/drain extensions and a third anneal at a temperature less than the second anneal.

Abstract translation: 一种改进深亚微米场效应晶体管和MOSFET的沟道掺杂分布的方法。 该方法涉及在不同温度下退火的双光晕植入物，以改善约50nm或更小的MOSFET的阈值电压滚降特性。 该方法包括深源/漏植入和退火，随后是斜角深晕植入和在较低温度下的第二退火。 然后制造非晶化植入物，随后是第二成角度的晕轮植入物，在低于第二次退火的温度下形成源极/漏极延伸部分和进行第三次退火。

公开(公告)号：US06551885B1

公开(公告)日：2003-04-22

申请号：US09779986

申请日：2001-02-09

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L21336

CPC classification number: H01L29/66772 ,  H01L29/458 ,  H01L29/66545 ,  H01L29/78618

Abstract: A method of manufacturing an integrated circuit utilizes a thin film substrate and a high-k gate dielectric. The method includes providing a mask structure on a top surface of the thin film, depositing a semiconductor material above the top surface of the thin film and the mask structure, removing the semiconductor material to a level below the top surface of the mask structure, siliciding the semiconductor material, and providing a gate structure in an aperture formed by removing the mask structure. The transistor can be a fully depleted transistor having material for siliciding source and drain regions.

Abstract translation: 集成电路的制造方法利用薄膜基板和高k栅极电介质。 该方法包括在薄膜的顶表面上提供掩模结构，在半导体材料的上表面和掩模结构之上沉积半导体材料，将半导体材料去除到掩模结构的顶表面以下的水平，硅化 半导体材料，并且通过去除掩模结构形成的孔中提供栅极结构。 晶体管可以是具有用于硅化源极和漏极区域的材料的完全耗尽的晶体管。

公开(公告)号：US06475890B1

公开(公告)日：2002-11-05

申请号：US09789939

申请日：2001-02-12

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L2144

CPC classification number: H01L29/7853 ,  H01L29/42384 ,  H01L29/66795

Abstract: For fabricating a field effect transistor on a semiconductor substrate in SOI (semiconductor on insulator) technology, a pillar of semiconductor material is formed on a layer of buried insulating material. The pillar has a top surface and first and second side surfaces, and the pillar has a width, a length, and a height. A masking structure is formed on a center portion of the top surface of the pillar along the length of the pillar. A top portion of the height of the pillar is etched from exposed surfaces of the top surface of the pillar down to a bottom portion of the height of the pillar to form an upside down T-shape for the pillar. A gate dielectric material is deposited on any exposed surface of the semiconductor material of the pillar for a gate length along the length of the pillar. A gate electrode material is deposited on the gate dielectric material to surround the pillar for the gate length of the pillar. A drain and source dopant is implanted into exposed regions of the pillar to form a drain of the field effect transistor on a first side of the gate electrode material along the length of the pillar and to form a source of the field effect transistor on a second side of the gate electrode material along the length of the pillar. In this manner, for a given height and width of the semiconductor pillar, any point of a cross-section of such a pillar is more closely located to the gate bias applied at a surface of such a pillar to maximize effective drive current while minimizing undesired short channel effects of the field effect transistor.

Abstract translation: 为了在SOI（绝缘体上半导体）技术的半导体衬底上制造场效应晶体管，在掩埋绝缘材料层上形成半导体材料柱。 支柱具有顶表面和第一和第二侧表面，并且柱具有宽度，长度和高度。 掩模结构沿着柱的长度形成在柱的顶表面的中心部分上。 柱的高度的顶部从柱的顶表面的暴露表面蚀刻到柱的高度的底部，以形成柱的上下颠倒的T形。 栅极电介质材料沉积在沿着柱的长度的栅极长度的柱的半导体材料的任何暴露的表面上。 栅极电极材料沉积在栅极电介质材料上以围绕柱的栅极长度的柱。 将漏极和源极掺杂剂注入到柱的暴露区域中，以在栅极电极材料的沿着该柱的长度的第一侧上形成场效应晶体管的漏极，并在第二个栅极晶体管的一端形成一个源极 沿着柱的长度的栅电极材料的侧面。 以这种方式，对于给定的半导体柱的高度和宽度，这种柱的横截面的任何点更接近于施加在这种柱的表面处的栅极偏置，以最大化有效的驱动电流，同时最小化不期望的 场效应晶体管的短通道效应。

公开(公告)号：US06459141B2

公开(公告)日：2002-10-01

申请号：US09495075

申请日：2000-01-31

Applicant: Bin Yu ,  Che-Hoo Ng

Inventor： Bin Yu ,  Che-Hoo Ng

IPC: H01L2904

CPC classification number: H01L21/26506 ,  H01L21/26513 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/092 ,  H01L29/1079

Abstract: The invention provides an improved well structure for electrically separating n-channel and p-channel MOSFETs. The invention first forms a shallow well in a substrate. A buried amorphous layer is then formed below the shallow well. A deep well is then formed below the buried amorphous layer. The substrate is then subjected to a rapid thermal anneal to recrystallize the buried amorphous layer. The well structure is formed by the shallow well and the deep well. A conventional semiconductor device may then be formed above the well structure. The buried amorphous layer suppresses the channeling effect during the forming of the deep well without requiring a tilt angle.

Abstract translation: 本发明提供了用于电分离n沟道和p沟道MOSFET的改进的阱结构。 本发明首先在基底中形成浅井。 然后在浅井下面形成掩埋非晶层。 然后在埋入的非晶层下方形成深井。 然后对衬底进行快速热退火以使埋入的非晶层重结晶。 井结构由浅井和深井组成。 然后可以在阱结构之上形成常规的半导体器件。 掩埋非晶层在形成深井期间抑制沟道效应，而不需要倾斜角。

公开(公告)号：US06441433B1

公开(公告)日：2002-08-27

申请号：US09824412

申请日：2001-04-02

Applicant: William G. En ,  Srinath Krishnan ,  Dong-Hyuk Ju ,  Bin Yu

Inventor： William G. En ,  Srinath Krishnan ,  Dong-Hyuk Ju ,  Bin Yu

IPC: H01L3113

CPC classification number: H01L29/66507 ,  H01L21/28518 ,  H01L29/41733 ,  H01L29/458 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66772 ,  H01L29/78603 ,  H01L29/78621 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A transistor device formed on a semiconductor-on-insulator (SOI) substrate with a buried oxide (BOX) layer disposed thereon and an active layer disposed on the BOX layer having active regions defined by isolation trenches. The device includes a gate defining a channel interposed between a source and a drain formed within the active region of the SOI substrate. Further, the device includes a multi-thickness silicide layer formed on the main source and drain regions and source and drain extension regions wherein a portion of the multi-thickness silicide layer which is formed on the source and drain extension regions is thinner than a portion of the silicide layer which is formed on the main source and drain regions. The device further includes a second thin silicide layer formed on a polysilicon electrode of the gate.

Abstract translation: 一种在绝缘体上半导体（SOI）衬底上形成的埋置氧化物（BOX）层的晶体管器件，以及设置在具有由隔离沟槽限定的有源区域的BOX层上的有源层。 该器件包括限定插入在SOI衬底的有源区域内形成的源极和漏极之间的沟道的栅极。 此外，器件包括形成在主源极和漏极区域以及源极和漏极延伸区域上的多层硅化物层，其中形成在源极和漏极延伸区域上的多层硅化物层的一部分比部分 形成在主源极和漏极区上的硅化物层。 该器件还包括形成在栅极的多晶硅电极上的第二薄硅化物层。

公开(公告)号：US06432784B1

公开(公告)日：2002-08-13

申请号：US09804162

申请日：2001-03-12

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L21336

CPC classification number: H01L29/66477 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/78

Abstract: The disclosure includes an exemplary embodiment which relates to a method of forming L-shaped spacers in an integrated circuit. This method can include providing a gate structure over a semiconductor substrate, depositing a spacer material adjacent lateral sides of the gate structure, forming dummy oxide spacer structures over the spacer material where the dummy oxide spacer structures are shaped to selectively cover an L-shaped portion of the spacer material, removing portions of the spacer material not covered by the dummy oxide spacer structures, and removing the dummy oxide spacer structures.

Abstract translation: 本公开包括一个示例性实施例，其涉及在集成电路中形成L形间隔物的方法。 该方法可以包括在半导体衬底上提供栅极结构，在栅极结构的侧面附近沉积间隔物材料，在间隔物材料上形成虚拟氧化物间隔物结构，其中虚拟氧化物间隔物结构被成形为选择性地覆盖L形部分 去除未被虚拟氧化物间隔物结构覆盖的间隔物材料的部分，以及去除虚拟氧化物间隔物结构。

公开(公告)号：US06420218B1

公开(公告)日：2002-07-16

申请号：US09559368

申请日：2000-04-24

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L21335

CPC classification number: H01L29/78696 ,  H01L29/458 ,  H01L29/66772 ,  H01L29/78618

Abstract: An ultra-large-scale integrated (ULSI) circuit includes MOSFETs on an SOI substrate. The MOSFETs include recessed source and drain regions. The recessed source and drain regions are formed utilizing an amorphous semiconductor layer. The recessed source and drain regions allow sufficient material for silicidation and yet allow an ultra thin channel region to be utilized. The channel region is above an insulative island.

Abstract translation: 超大规模集成（ULSI）电路包括SOI衬底上的MOSFET。 MOSFET包括凹陷的源极和漏极区域。 凹陷的源极和漏极区域利用非晶半导体层形成。 凹陷的源极和漏极区域允许足够的硅化物材料，并允许利用超薄沟道区域。 通道区域在绝缘岛之上。