公开(公告)号：US20020141241A1

公开(公告)日：2002-10-03

申请号：US10068565

申请日：2002-02-05

Applicant: STMicroelectronics S.r.I.

Inventor： Irene Babudri ,  Mauro Giacomini

IPC: G11C016/26

CPC classification number: G11C29/24 ,  G11C16/28

Abstract: A memory device implements a reading operation that comprises: providing first and second additional memory cells whose threshold voltage values correspond to a maximum value and a minimum value of a distribution of threshold voltages of a cell array of the memory device; programming the first and second additional memory cells with predetermined first and second logic values; simultaneously reading a logic contents of the first and second additional memory cells, and data to be read in the cell array; comparing the logic contents of the first and second additional memory cells, as read during the reading step, with the first and second predetermined logic values; generating a result signal of the comparison step, such a result signal having a first value in the event of the logic contents of the first and second additional memory cells, as read during the reading step, matching the first and second predetermined logic values, respectively, and having a second value in the event of the logic contents of the first and second additional memory cells, as read during the reading step, failing to match the first and second predetermined logic values, respectively.

Abstract translation: 存储器件实现读取操作，其包括：提供其阈值电压值对应于存储器件的单元阵列的阈值电压分布的最大值和最小值的第一和第二附加存储器单元; 以预定的第一和第二逻辑值对第一和第二附加存储器单元进行编程; 同时读取第一和第二附加存储器单元的逻辑内容以及要在单元阵列中读取的数据; 将在读取步骤期间读取的第一和第二附加存储器单元的逻辑内容与第一和第二预定逻辑值进行比较; 生成比较步骤的结果信号，在读取步骤期间读取第一和第二附加存储器单元的逻辑内容的情况下具有第一值的结果信号分别与第一和第二预定逻辑值相匹配 并且在读取步骤期间读取的第一和第二附加存储器单元的逻辑内容的第二值分别不匹配第一和第二预定逻辑值。

公开(公告)号：US20020094665A1

公开(公告)日：2002-07-18

申请号：US10068108

申请日：2002-02-05

Applicant: STMicroelectronics S.r.I

Inventor： Flavio Villa ,  Gabriele Barlocchi ,  Pietro Montanini

IPC: H01L021/20

CPC classification number: H01L21/3065 ,  H01L21/76248 ,  H01L21/76294

Abstract: Method for manufacturing an SOI wafer. On a monocrystalline silicon wafer, forming protective regions having the shape of an overturned U, made of an oxidation resistant material, the protective regions covering first wafer portions. Forming deep trenches in the wafer which extend between, and laterally delimit the first wafer portions, completely oxidizing the first wafer portions except their upper areas which are covered by the protective regions, to form at least one continuous region of covered oxide overlaid by the non-oxidized upper portions. Removing the protective regions, and epitaxially growing a crystalline semiconductor material layer from the non-oxidized upper portions.

Abstract translation: SOI晶片的制造方法。 在单晶硅晶片上，形成由抗氧化材料制成的具有翻转U形状的保护区域，保护区域覆盖第一晶片部分。 在晶片中形成深沟槽，其在第一晶片部分之间延伸并横向限定第一晶片部分，除了被保护区域覆盖的上部区域之外，完全氧化第一晶片部分，以形成至少一个覆盖氧化物的连续区域， 氧化上部。 去除保护区域，并从非氧化的上部部分外延生长结晶半导体材料层。

公开(公告)号：US20020089317A1

公开(公告)日：2002-07-11

申请号：US10008540

申请日：2001-11-07

Applicant: STMicroelectronics S.r.I.

Inventor： Osama Khouri ,  Ilaria Motta ,  Rino Micheloni ,  Guido Torelli

IPC: G05F001/40

CPC classification number: G05F1/56

Abstract: A voltage regulator having a comparator with an output terminal that is the output of the regulator, terminals for connection to a voltage supply, a source of a reference voltage connected to an input terminal of the comparator, and a feedback circuit connected between the output terminal and the other input terminal of the comparator. To prevent transients upon the transition from the standby state to the active state, there is provided a second reference-voltage source that provides a reference voltage substantially equal to that of the first source, a switch for connecting the second source to the other input terminal of the comparator, and a control circuit that can activate the supply of the regulator and can close the switch for a predetermined period of time when the supply of the regulator is activated.

Abstract translation: 一种电压调节器，具有比较器，输出端子是调节器的输出端子，用于连接到电压源的端子，连接到比较器的输入端子的参考电压源，以及连接在输出端子之间的反馈电路 和比较器的另一个输入端。 为了防止从待机状态转换到活动状态的瞬变，提供了提供基本上等于第一源的参考电压的第二参考电压源，用于将第二源连接到另一个输入端的开关 的控制电路，以及控制电路，其能够启动调节器的供应并且可以在调节器的供应被激活时将开关闭合预定的一段时间。

公开(公告)号：US20020067640A1

公开(公告)日：2002-06-06

申请号：US09972769

申请日：2001-10-05

Applicant: STMicroelectronics S.r.I.

Inventor： Luigi Pascucci

IPC: G11C016/04

CPC classification number: G11C7/1042 ,  G11C8/12 ,  G11C16/08

Abstract: A semiconductor memory architecture having two memory banks each containing respective memory locations, and for each memory bank, respective circuits for selecting the locations of the bank and respective circuits for reading the data contained in the selected locations of the bank, a structure for the transfer of the data read by the reading circuits associated with the memory banks to data output terminals of the memory, there being a single data-transfer structure assigned selectively to one memory bank at a time and which includes storage for storing the most recent datum read by the reading circuits, and output driver circuits activated selectively in order to transfer the contents of the registers to the data output terminals of the memory, an addressing structure having, for each memory bank, and a respective circuit for the sequential scanning of the memory locations of the bank, operatively connected to the respective circuits for selecting the locations of the memory bank.

Abstract translation: 一种半导体存储器架构，其具有两个存储体，每个存储体各自包含相应的存储器位置，并且对于每个存储体，各个电路用于选择存储体的位置以及用于读取包含在存储体的选定位置中的数据的相应电路，转移结构 由与存储体相关联的读取电路读取的数据读取到存储器的数据输出端，存在一次分配给一个存储体的单个数据传输结构，其中包括存储用于存储最近的数据读取的存储器 读取电路和输出驱动器电路被选择性地激活，以将寄存器的内容传送到存储器的数据输出端，对于每个存储体，具有用于存储器位置的顺序扫描的寻址结构 ，可操作地连接到相应的电路以选择存储体的位置。

公开(公告)号：US20020063573A1

公开(公告)日：2002-05-30

申请号：US09948144

申请日：2001-09-06

Applicant: STMicroelectronics S.r.I.

Inventor： Angelo Genova ,  Roberto Gariboldi ,  Aldo Novelli ,  Giulio Ricotti

IPC: G01R031/26

CPC classification number: G01R19/16519 ,  H02M2001/0009

Abstract: The device and method monitor the current delivered to a load through a power transistor including a sense transistor. The circuit includes a disturbances attenuating circuit that has a differential stage, and first, second and third stages referenced to ground, the respective input nodes of which are connected in common to an output node of the differential stage. The third stage is formed by a transistor identical to a transistor of the first stage and delivers a current signal through a current terminal thereof, proportional to the current being delivered to the load.

Abstract translation: 该装置和方法通过包括检测晶体管的功率晶体管来监测传送到负载的电流。 该电路包括具有差分级的干扰衰减电路，以及参考地的第一，第二和第三级，其各个输入节点共同连接到差分级的输出节点。 第三级由与第一级的晶体管相同的晶体管形成，并将电流信号通过其电流端与传递给负载的电流成比例。

公开(公告)号：US20020063307A1

公开(公告)日：2002-05-30

申请号：US09991555

申请日：2001-11-21

Applicant: STMicroelectronics S.r.I.

Inventor： Davide Patti

IPC: H01L027/01 ,  H01L027/12 ,  H01L031/0392 ,  H01L029/76 ,  H01L031/062 ,  H01L029/94 ,  H01L031/119 ,  H01L021/20 ,  H01L029/00 ,  H01L023/62 ,  H01L031/113 ,  H01L027/082 ,  H01L027/102 ,  H01L029/70 ,  H01L031/11

CPC classification number: H01L28/20 ,  H01L27/0802 ,  H01L29/8605

Abstract: A structure for a semiconductor resistive element, applicable in particular to power components, having a high concentration substrate of the n type, a first epitaxial layer of the n type, a region of the p type arranged on said first epitaxial layer so to form the resistive element proper, a second epitaxial layer of n type grown on said first epitaxial layer to make the region of the p type a buried region, and an additional layer of the n type with a higher concentration with respect to the second epitaxial level, positioned on the embedded region. Low resistivity regions of the p type adapted to make low resistivity deep contacts for the resistor are provided. The buried region can be made either with a development that is substantially uniform in its main direction of extension or so to present, at on part of its length, a structure of adjacent subregions in marginal continuity. In this way, either a resistive element presenting a substantially linear performance in all ranges of applied voltage or a resistive element presenting a marked increase of the resistance value as the applied voltage increases can be made. This all with the additional possibility of selectively varying the resistance value demonstrated before the increase.

Abstract translation: 一种用于半导体电阻元件的结构，特别适用于具有n型高浓度衬底，n型第一外延层，布置在所述第一外延层上的p型区域的功率元件，从而形成 电阻元件本体，在所述第一外延层上生长以使p型区域成为掩埋区域的n型第二外延层和相对于第二外延级别具有较高浓度的n型附加层，定位 在嵌入式区域。 提供适于为电阻器制造低电阻率深触点的p型低电阻率区域。 掩埋区域可以通过在其主要延伸方向上基本均匀的发展来实现，或者在其长度的一部分上呈现边缘连续性的相邻子区域的结构。 以这种方式，可以在所施加的电压的所有范围内呈现基本上线性的电阻元件，或者施加的电压增加时呈现电阻值的显着增加的电阻元件。 这一切都具有选择性地改变在增加之前显示的电阻值的附加可能性。

公开(公告)号：US20020054504A1

公开(公告)日：2002-05-09

申请号：US09957628

申请日：2001-09-19

Applicant: STMicroelectronics S.r.I.

Inventor： Rino Micheloni ,  Giovanni Campardo

IPC: G11C016/04

CPC classification number: G11C11/5621 ,  G11C16/0416 ,  G11C2211/5641

Abstract: The multilevel memory device has a memory section containing cells that can be programmed with a predetermined number of levels greater than two, i.e., a multilevel array, and a memory section containing cells that can be programmed with two levels, i.e., a bilevel array. The multilevel array is used for storing high-density data, for which speed of reading is not essential, for example for storing the operation code of the system including the memory device. On the other hand, the bilevel array is used for storing data for which high speed and reliability of reading is essential, such as the BIOS of personal computers, and the data to be stored in a cache memory. The circuitry parts dedicated to programming, writing of test instructions, and all the functions necessary for the operation of the memory device, can be common to both arrays.

Abstract translation: 多电平存储器件具有存储器部分，该存储器部分包含可以以大于2的预定数量的级别（即，多级阵列）编程的单元，以及包含可以用两个级别编程的单元的存储器部分，即双层阵列。 多级阵列用于存储高密度数据，读取速度不是必需的，例如用于存储包括存储器件的系统的操作代码。 另一方面，双层阵列用于存储读取的高速度和可靠性至关重要的数据，例如个人计算机的BIOS以及要存储在高速缓冲存储器中的数据。 专用于编程，写入测试指令的电路部分以及存储器件操作所需的所有功能对于这两个阵列都是共同的。

公开(公告)号：US20020047694A1

公开(公告)日：2002-04-25

申请号：US09955735

申请日：2001-09-18

Applicant: STMicroelectronics S.r.I.

Inventor： Alessandro Zafarana ,  Claudia Castelli

IPC: G05F001/40

CPC classification number: H02M3/1584 ,  H02M2001/0009

Abstract: A voltage/current controller device, particularly for interleaving switching regulators, comprises: a DC/DC converter having a plurality of modules, with each module including a drive transistor pair connected in series between first and second supply voltage references, a current sensor connected to one transistor in the pair, and a current read circuit connected to the sensor. Advantageously, the read circuit comprises a transconductance amplifier connected across the current sensor to sense a voltage signal related to a load current being applied to each module, the transconductance amplifier reading the voltage signal with the transistor in the conducting state.

Abstract translation: 电压/电流控制器装置，特别是用于交错开关稳压器的电压/电流控制器装置包括：具有多个模块的DC / DC转换器，每个模块包括串联连接在第一和第二电源电压基准之间的驱动晶体管对，连接到 该对中的一个晶体管和连接到传感器的电流读取电路。 有利地，读取电路包括跨过电流传感器连接的跨导放大器，以感测与施加到每个模块的负载电流相关的电压信号，跨导放大器在晶体管处于导通状态下读取电压信号。

公开(公告)号：US20020036487A1

公开(公告)日：2002-03-28

申请号：US09912232

申请日：2001-07-24

Applicant: STMicroelectronics S.r.I.

Inventor： Ugo Moriconi ,  Claudio Adragna

IPC: G05F001/44

CPC classification number: H03K17/063 ,  H02M3/155

Abstract: Disclosed is a bootstrap circuit in DC/DC static converters having the characteristic of comprising a fixed frequency signal, a recharge circuit of a capacitor and current generator means, said generator means controlled so as to emit current pulses, in synchrony with said fixed frequency signal, of a predetermined duration, every time that charge accumulated by said capacitor goes below a predetermined level.

Abstract translation: 公开了一种DC / DC静态转换器中的自举电路，具有包括固定频率信号，电容器的再充电电路和电流发生器装置的特性，所述发生器装置被控制以与所述固定频率信号同步地发射电流脉冲 每当所述电容器累积的电荷低于预定电平时，具有预定持续时间。

公开(公告)号：US20010017564A1

公开(公告)日：2001-08-30

申请号：US09751927

申请日：2000-12-29

Applicant: STMicroelectronics S.r.I.

Inventor： Michelangelo Mazzucco ,  Vanni Poletto ,  Melano Carlo Lorenzo Protti

IPC: G06G007/18

CPC classification number: G01L23/225 ,  G06J1/00

Abstract: A circuit extends the output voltage range of an integrator circuit wherein the input signal is used to produce an output signal, and the voltage of the output signal develops monotonically within a predetermined range of possible values. The integrator circuit is driven within an integration time period such that each time the signal at its output reaches a limit of the range of values, the integrator circuit starts a subsequent integration stage of the input signal in which the output signal develops again within the above-mentioned range. This takes place by resetting the integrator circuit or by a reversal of the characteristic slope of the output signal. This is combined with storing the number of occasions on which these interventions have occurred as determined by a counter. This enables the actual voltage value of the signal resulting from the integration to be calculated by a relatively straightforward mathematical operation from the reading of the counter, and from the signal currently present at the output of the integrator at the end of the integration period.

Abstract translation: 电路扩展积分器电路的输出电压范围，其中输入信号用于产生输出信号，并且输出信号的电压在可能值的预定范围内单调发展。 积分电路在积分时间段内被驱动，使得每当其输出端的信号达到值范围的极限时，积分器电路开始输入信号的后续积分级，其中输出信号在上述范围内再次产生 提到的范围。 这通过复位积分器电路或反转输出信号的特性斜率来进行。 这与存储由柜台确定的这些干预发生的场合的数量相结合。 这使得通过来自计数器的读数的相对简单的数学运算以及在积分周期结束时当前存在于积分器的输出端的信号来计算由积分产生的信号的实际电压值。