公开(公告)号：US20210080500A1

公开(公告)日：2021-03-18

申请号：US16573946

申请日：2019-09-17

Applicant: Intel Corporation

Inventor： Henning Braunisch ,  Aleksandar Aleksov ,  Veronica Strong ,  Brandon Rawlings ,  Johanna Swan ,  Shawna Liff

IPC: G01R31/28 ,  G01K7/42

Abstract: An integrated circuit package having an electronic interposer comprising an upper section, a lower section and a middle section, a die side integrated circuit device electrically attached to the upper section of the electronic interposer, a die side heat dissipation device thermally contacting the die side integrated circuit device, a land side integrated circuit device electrically attached to the lower section of the electronic interposer, and a land side heat dissipation device thermally contacting the at least one die side integrated circuit device. The upper section and the lower section may each have between two and four layers and the middle section may be formed between the upper section and the lower section, and comprises up to eight layers, wherein a thickness of each layer of the middle section is thinner than a thickness of any of the layers of the upper section and the lower section.

公开(公告)号：US20210074620A1

公开(公告)日：2021-03-11

申请号：US16564168

申请日：2019-09-09

Applicant: Intel Corporation

Inventor： Johanna Swan ,  Henning Braunisch ,  Aleksandar Aleksov ,  Shawna Liff ,  Brandon Rawlings ,  Veronica Strong

IPC: H01L23/498 ,  G03F1/54 ,  G03F1/68 ,  G03F1/38

Abstract: An lithographic reticle may be formed comprising a transparent substrate, a substantially opaque mask formed on the transparent substrate that defines at least one exposure window, wherein the at least one exposure window has a first end, a first filter formed on the transparent substrate within the at least one exposure window and abutting the first end thereof, and a second filter formed on the transparent substrate within the at least one exposure window and abutting the first filter, wherein an average transmissivity of the first filter is substantially one half of a transmissivity of the second filter. In another embodiment, the at least one exposure window includes a third filter abutting the second end and is adjacent the second filter. Further embodiments of the present description include interconnection structures and systems fabricated using the lithographic reticle.

公开(公告)号：US20210044030A1

公开(公告)日：2021-02-11

申请号：US16534820

申请日：2019-08-07

Applicant: Intel Corporation

Inventor： Aleksandar Aleksov ,  Feras Eid ,  Georgios Dogiamis ,  Telesphor Kamgaing ,  Johanna M. Swan

IPC: H01Q23/00 ,  H01Q1/52 ,  H01Q1/02

Abstract: Embodiments may relate to a radio frequency (RF) multi-chip module that includes a first RF die and a second RF die. The first and second RF dies may be coupled with a package substrate at an inactive side of the respective dies. A bridge may be coupled with an active side of the first and second RF dies die such that the first and second RF dies are communicatively coupled through the bridge, and such that the first and second RF dies are at least partially between the package substrate and the bridge. Other embodiments may be described or claimed.

公开(公告)号：US20200321281A1

公开(公告)日：2020-10-08

申请号：US16904363

申请日：2020-06-17

Applicant: Intel Corporation

Inventor： Aleksandar Aleksov ,  Adel A. Elsherbini ,  Kristof Darmawikarta ,  Robert A. May ,  Sri Ranga Sai Boyapati

IPC: H01L23/538 ,  H01L25/18 ,  H01L25/065 ,  H01L21/48 ,  H01L23/00 ,  H01L23/31 ,  H01L25/00 ,  H01L23/498

Abstract: An apparatus is provided which comprises: a plurality of first conductive contacts having a first pitch spacing on a substrate surface, a plurality of second conductive contacts having a second pitch spacing on the substrate surface, and a plurality of conductive interconnects disposed within the substrate to couple a first grouping of the plurality of second conductive contacts associated with a first die site with a first grouping of the plurality of second conductive contacts associated with a second die site and to couple a second grouping of the plurality of second conductive contacts associated with the first die site with a second grouping of the plurality of second conductive contacts associated with the second die site, wherein the conductive interconnects to couple the first groupings are present in a layer of the substrate above the conductive interconnects to couple the second groupings. Other embodiments are also disclosed and claimed.

公开(公告)号：US20200294940A1

公开(公告)日：2020-09-17

申请号：US16397923

申请日：2019-04-29

Applicant: Intel Corporation

Inventor： Georgios Dogiamis ,  Aleksandar Aleksov ,  Adel A. Elsherbini ,  Henning Braunisch ,  Johanna M. Swan ,  Telesphor Kamgaing

IPC: H01L23/66 ,  G02B6/30 ,  H01P11/00 ,  H01P3/16

Abstract: Embodiments may relate to a semiconductor package that includes a package substrate coupled with a die. The package may further include a waveguide coupled with the first package substrate. The waveguide may include two or more layers of a dielectric material with a waveguide channel positioned between two layers of the two or more layers of the dielectric material. The waveguide channel may convey an electromagnetic signal with a frequency greater than 30 gigahertz (GHz). Other embodiments may be described or claimed.

公开(公告)号：US10741534B2

公开(公告)日：2020-08-11

申请号：US16145620

申请日：2018-09-28

Applicant: Intel Corporation

Inventor： Aleksandar Aleksov ,  Sri Ranga Sai Boyapati ,  Kristof Darmawikarta ,  Rahul N. Manepalli ,  Robert Alan May ,  Srinivas V. Pietambaram

IPC: H01L25/18 ,  H01L23/00 ,  H01L23/538 ,  H01L23/373

Abstract: The present description addresses example methods for forming multi-chip microelectronic devices and the resulting devices. The multiple semiconductor die of the multichip package will be attached to a solid plate with a bonding system selected to withstand stresses applied when a mold material is applied to encapsulate the die of the multichip device. The solid plate will remain as a portion of the finished multi-chip device. The solid plate can be a metal plate to function as a heat spreader for the completed multi-chip device.

公开(公告)号：US10727185B2

公开(公告)日：2020-07-28

申请号：US16329644

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Aleksandar Aleksov ,  Adel A. Elsherbini ,  Kristof Darmawikarta ,  Robert A. May ,  Sri Ranga Sai Boyapati

IPC: H01L23/34 ,  H01L23/538 ,  H01L25/18 ,  H01L25/065 ,  H01L21/48 ,  H01L23/00 ,  H01L23/31 ,  H01L25/00 ,  H01L23/498 ,  H01L21/56

Abstract: An apparatus is provided which comprises: a plurality of first conductive contacts having a first pitch spacing on a substrate surface, a plurality of second conductive contacts having a second pitch spacing on the substrate surface, and a plurality of conductive interconnects disposed within the substrate to couple a first grouping of the plurality of second conductive contacts associated with a first die site with a first grouping of the plurality of second conductive contacts associated with a second die site and to couple a second grouping of the plurality of second conductive contacts associated with the first die site with a second grouping of the plurality of second conductive contacts associated with the second die site, wherein the conductive interconnects to couple the first groupings are present in a layer of the substrate above the conductive interconnects to couple the second groupings. Other embodiments are also disclosed and claimed.

公开(公告)号：US10685949B2

公开(公告)日：2020-06-16

申请号：US15450900

申请日：2017-03-06

Applicant: Intel Corporation

Inventor： Aleksandar Aleksov ,  Mauro Kobrinsky ,  Johanna Swan ,  Rajendra C. Dias

IPC: H01L25/00 ,  H05K1/14 ,  H01L23/00 ,  H05K1/02 ,  H05K1/03 ,  H05K1/11 ,  H05K3/46

Abstract: Generally discussed herein are systems and apparatuses that can include apparatuses, systems, or method for a flexible, wire bonded device. According to an example an apparatus can include (1) a first rigid circuit comprising a first plurality of bond pads proximate to a first edge of the first rigid circuit, (2) a second rigid circuit comprising a second plurality of bond pads proximate to a first edge of the second rigid circuit, the second rigid circuit adjacent the first rigid circuit and the first edge of the second rigid circuit facing the first edge of the first rigid circuit, or (3) a first plurality of wire bonded wires, each wire bonded wire of the first plurality of wire bonded wires electrically and mechanically connected to a bond pad of the first plurality of bond pads and a bond pad of the second plurality of bond pads.

公开(公告)号：US20200006235A1

公开(公告)日：2020-01-02

申请号：US16020295

申请日：2018-06-27

Applicant: Intel Corporation

Inventor： Aleksandar Aleksov ,  Johanna M. Swan

IPC: H01L23/538 ,  H01L25/18 ,  H01L23/13 ,  H01L25/00 ,  H01L21/48 ,  H01L23/66

Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a high bandwidth interconnect, a first interposer having high bandwidth circuitry coupled to the package substrate, wherein the high bandwidth circuitry of the first interposer is electrically coupled to the high bandwidth interconnect, and a second interposer having high bandwidth circuitry coupled to the package substrate, wherein the high bandwidth circuitry of the second interposer is electrically coupled to the high bandwidth interconnect, and wherein the first interposer is electrically coupled to the second interposer via the high bandwidth interconnect.

公开(公告)号：US10468357B2

公开(公告)日：2019-11-05

申请号：US15546958

申请日：2015-03-11

Applicant: Intel Corporation

Inventor： Rajendra C. Dias ,  Tatyana N. Andryushchenko ,  Mauro J. Kobrinsky ,  Aleksandar Aleksov ,  David W. Staines

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/16 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31

Abstract: Embodiments of the invention include a microelectronic device and methods for forming a microelectronic device. In an embodiment, the microelectronic device includes a semiconductor die that has one or more die contacts that are each electrically coupled to a contact pad by a conductive trace. The semiconductor die may have a first elastic modulus. The microelectronic device may also include an encapsulation layer over the semiconductor die and the conductive trace. The encapsulation layer may have a second elastic modulus that is less than the first elastic modulus. The microelectronic device may also include a first strain redistribution layer within the encapsulation layer. The first strain redistribution layer may have a footprint that covers the semiconductor die and a portion of the conductive traces. The strain redistribution layer may have a third elastic modulus that is less than the first elastic modulus and greater than the second elastic modulus.