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    Semiconductor device with reduced junction leakage and an associated method of forming such a semiconductor device
    253.
    发明授权
    Semiconductor device with reduced junction leakage and an associated method of forming such a semiconductor device 失效
    具有减小的结漏电的半导体器件和形成这种半导体器件的相关方法

    公开(公告)号：US08349716B2

    公开(公告)日：2013-01-08

    申请号：US12911186

    申请日：2010-10-25

    Applicant: Ming Cai ,  Christian Lavoie ,  Ahmet S. Ozcan ,  Bin Yang ,  Zhen Zhang

    Inventor： Ming Cai ,  Christian Lavoie ,  Ahmet S. Ozcan ,  Bin Yang ,  Zhen Zhang

    IPC: H01L21/336 ,  H01L21/04

    CPC classification number: H01L21/2257 ,  H01L21/28512 ,  H01L21/28518 ,  H01L29/665 ,  H01L29/66643

    Abstract: Disclosed is a semiconductor device having a p-n junction with reduced junction leakage in the presence of metal silicide defects that extend to the junction and a method of forming the device. Specifically, a semiconductor layer having a p-n junction is formed. A metal silicide layer is formed on the semiconductor layer and a dopant is implanted into the metal silicide layer. An anneal process is performed causing the dopant to migrate toward the metal silicide-semiconductor layer interface such that the peak concentration of the dopant will be within a portion of the metal silicide layer bordering the metal silicide-semiconductor layer interface and encompassing the defects. As a result, the silicide to silicon contact is effectively engineered to increase the Schottky barrier height at the defect, which in turn drastically reduces any leakage that would otherwise occur, when the p-n junction is in reverse polarity.

    Abstract translation: 公开了一种具有p-n结的半导体器件，其在存在延伸到结的金属硅化物缺陷的情况下具有减少的结漏电以及形成器件的方法。 具体地说，形成具有p-n结的半导体层。 在半导体层上形成金属硅化物层，并且将掺杂剂注入到金属硅化物层中。 执行退火处理，使掺杂剂朝向金属硅化物半导体层界面迁移，使得掺杂剂的峰值浓度将在金属硅化物层的与金属硅化物半导体层界面接壤并包围缺陷的部分内。 结果，硅化物与硅接触被有效地设计以增加缺陷处的肖特基势垒高度，这反过来大大降低了当p-n结处于相反极性时将会发生的任何泄漏。

    LED lamp
    255.
    发明授权
    LED lamp 失效
    点灯

    公开(公告)号：US08220956B2

    公开(公告)日：2012-07-17

    申请号：US12690251

    申请日：2010-01-20

    Applicant: Chih-Ming Lai ,  Hong-Bin Yang ,  Ming-Young Shiao

    Inventor： Chih-Ming Lai ,  Hong-Bin Yang ,  Ming-Young Shiao

    IPC: F21S4/00

    CPC classification number: F21V19/0045 ,  F21K9/272 ,  F21Y2103/10 ,  F21Y2107/30 ,  F21Y2107/90 ,  F21Y2115/10

    Abstract: An LED lamp includes an envelope, two covers, a mounting board and a plurality of LEDs. The covers engages with opposite ends of the envelope. Each of the covers has an electrically conductive part. The mounting board is received in the envelope. Two ends of the mounting board electrically connect with the electrically conductive parts of the two covers, respectively. The LEDs are disposed on the mounting board and received in the envelope.

    Abstract translation: LED灯包括外壳，两个盖，安装板和多个LED。 盖子与信封的两端接合。 每个盖具有导电部分。 安装板接收在信封中。 安装板的两端分别与两个盖的导电部分电连接。 LED设置在安装板上并接收在信封中。

    Semiconductor device fabrication method for improved isolation regions and defect-free active semiconductor material
    256.
    发明授权
    Semiconductor device fabrication method for improved isolation regions and defect-free active semiconductor material 有权
    用于改进隔离区域和无缺陷活性半导体材料的半导体器件制造方法

    公开(公告)号：US08198170B2

    公开(公告)日：2012-06-12

    申请号：US12905805

    申请日：2010-10-15

    Applicant: Man Fai Ng ,  Bin Yang

    Inventor： Man Fai Ng ,  Bin Yang

    IPC: H01L21/762

    CPC classification number: H01L21/76224 ,  H01L21/76283 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/84

    Abstract: A fabrication method for a semiconductor device structure is provided. The device structure has a layer of silicon and a layer of silicon dioxide overlying the layer of silicon, and the method begins by forming an isolation recess by removing a portion of the silicon dioxide and a portion of the silicon. The isolation recess is filled with stress-inducing silicon nitride and, thereafter, the silicon dioxide is removed such that the stress-inducing silicon nitride protrudes above the silicon. Next, the exposed silicon is thermally oxidized to form silicon dioxide hardmask material overlying the silicon. Thereafter, a first portion of the silicon dioxide hardmask material is removed to reveal an accessible surface of the silicon, while leaving a second portion of the silicon dioxide hardmask material intact. Next, silicon germanium is epitaxially grown from the accessible surface of the silicon.

    Abstract translation: 提供了半导体器件结构的制造方法。 该器件结构具有一层硅层和一层覆盖硅层的二氧化硅层，该方法开始于通过去除一部分二氧化硅和一部分硅来形成隔离凹槽。 隔离凹部填充有应力诱导性氮化硅，然后去除二氧化硅，使得应力诱导性氮化硅突出于硅上方。 接下来，暴露的硅被热氧化以形成覆盖在硅上的二氧化硅硬掩模材料。 此后，去除二氧化硅硬掩模材料的第一部分以露出硅的可接近表面，同时留下二氧化硅硬掩模材料的第二部分完好无损。 接下来，从硅的可接近表面外延生长硅锗。

    GLUCAGON ANTAGONISTS
    259.
    发明申请
    GLUCAGON ANTAGONISTS 有权

    公开(公告)号：US20120122783A1

    公开(公告)日：2012-05-17

    申请号：US12739342

    申请日：2008-10-23

    Applicant: Richard D. Dimarchi ,  Bin Yang

    Inventor： Richard D. Dimarchi ,  Bin Yang

    IPC: A61K38/26 ,  A61P3/10 ,  C07K14/605

    CPC classification number: C07K14/605 ,  A61K38/00

    Abstract: Glucagon antagonists are provided which comprise amino acid substitutions and/or chemical modifications to glucagon sequence. In one embodiment, the glucagon antagonists comprise a native glucagon peptide that has been modified by the deletion of the first two to five amino acid residues from the N-terminus and (i) an amino acid substitution at position 9 (according to the numbering of native glucagon) or (ii) substitution of the Phe at position 6 (according to the numbering of native glucagon) with phenyl lactic acid (PLA). In another embodiment, the glucagon antagonists comprise the structure A-B-C as described herein, wherein A is PLA, an oxy derivative thereof, or a peptide of 2-6 amino acids in which two consecutive amino acids of the peptide are linked via an ester or ether bond.

    Abstract translation: 提供了包含对胰高血糖素序列的氨基酸取代和/或化学修饰的胰高血糖素拮抗剂。 在一个实施方案中，胰高血糖素拮抗剂包含通过从N-末端缺失前两个至五个氨基酸残基而修饰的天然胰高血糖素肽，以及（i）在第9位的氨基酸取代（根据 天然胰高血糖素）或（ii）用苯基乳酸（PLA）取代第6位的Phe（根据天然胰高血糖素的编号）。 在另一个实施方案中，胰高血糖素拮抗剂包含如本文所述的结构ABC，其中A是PLA，其氧衍生物或2-6个氨基酸的肽，其中肽的两个连续氨基酸经由酯或醚连接 键。

    SEMICONDUCTOR DEVICE WITH REDUCED JUNCTION LEAKAGE AND AN ASSOCIATED METHOD OF FORMING SUCH A SEMICONDUCTOR DEVICE
    260.
    发明申请
    SEMICONDUCTOR DEVICE WITH REDUCED JUNCTION LEAKAGE AND AN ASSOCIATED METHOD OF FORMING SUCH A SEMICONDUCTOR DEVICE 失效
    具有降低接合泄漏的半导体器件和形成这种半导体器件的相关方法

    公开(公告)号：US20120098042A1

    公开(公告)日：2012-04-26

    申请号：US12911186

    申请日：2010-10-25

    Applicant: Ming Cai ,  Christian Lavoie ,  Ahmet S. Ozcan ,  Bin Yang ,  Zhen Zhang

    Inventor： Ming Cai ,  Christian Lavoie ,  Ahmet S. Ozcan ,  Bin Yang ,  Zhen Zhang

    IPC: H01L29/78 ,  H01L21/336 ,  H01L21/04

    CPC classification number: H01L21/2257 ,  H01L21/28512 ,  H01L21/28518 ,  H01L29/665 ,  H01L29/66643

    Abstract: Disclosed is a semiconductor device having a p-n junction with reduced junction leakage in the presence of metal silicide defects that extend to the junction and a method of forming the device. Specifically, a semiconductor layer having a p-n junction is formed. A metal silicide layer is formed on the semiconductor layer and a dopant is implanted into the metal silicide layer. An anneal process is performed causing the dopant to migrate toward the metal silicide-semiconductor layer interface such that the peak concentration of the dopant will be within a portion of the metal silicide layer bordering the metal silicide-semiconductor layer interface and encompassing the defects. As a result, the silicide to silicon contact is effectively engineered to increase the Schottky barrier height at the defect, which in turn drastically reduces any leakage that would otherwise occur, when the p-n junction is in reverse polarity.

    Abstract translation: 公开了一种具有p-n结的半导体器件，其在存在延伸到结的金属硅化物缺陷的情况下具有减少的结漏电以及形成器件的方法。 具体地说，形成具有p-n结的半导体层。 在半导体层上形成金属硅化物层，并且将掺杂剂注入到金属硅化物层中。 执行退火处理，使掺杂剂朝向金属硅化物半导体层界面迁移，使得掺杂剂的峰值浓度将在金属硅化物层的与金属硅化物半导体层界面接壤并包围缺陷的部分内。 结果，硅化物与硅接触被有效地设计以增加缺陷处的肖特基势垒高度，这反过来大大降低了当p-n结处于相反极性时将会发生的任何泄漏。

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