公开(公告)号：US20170074938A1

公开(公告)日：2017-03-16

申请号：US15359785

申请日：2016-11-23

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Lee D. Whetsel

IPC: G01R31/317 ,  G01R31/3177

CPC classification number: G01R31/31723 ,  G01R31/2851 ,  G01R31/3172 ,  G01R31/31724 ,  G01R31/3173 ,  G01R31/3177 ,  G01R31/318563 ,  G01R31/318575

Abstract: An integrated circuit includes combinational logic with flip-flops, parallel scan paths with a scan input for receiving test stimulus data to be applied to the combinational logic, combinational connections with the combinational logic for applying stimulus data to the combinational logic and receiving response data from the combinational logic, a scan output for transmitting test response data obtained from the combinational logic, and control inputs having an enable input and a select input for operating the parallel scan paths, each scan path includes flip-flops of the combinational logic that, in a test mode, are connected in series, compare circuitry indicates the result of a comparison of the received test response data and the expected data at a fail flag output, and one of the scan paths includes a scan cell having an input coupled to the fail flag output.

Abstract translation: 集成电路包括具有触发器的组合逻辑，具有用于接收要应用于组合逻辑的测试激励数据的扫描输入的并行扫描路径，与组合逻辑的组合连接，用于将刺激数据应用于组合逻辑并从 组合逻辑，用于发送从组合逻辑获得的测试响应数据的扫描输出以及具有用于操作并行扫描路径的使能输入和选择输入的控制输入，每个扫描路径包括组合逻辑的触发器， 测试模式串联连接，比较电路表示接收到的测试响应数据与故障标志输出的期望数据的比较结果，其中一个扫描路径包括具有耦合到故障的输入的扫描单元 标志输出。

公开(公告)号：US20170074936A1

公开(公告)日：2017-03-16

申请号：US15359073

申请日：2016-11-22

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Lee D. Whetsel

IPC: G01R31/317 ,  G01R31/3177

CPC classification number: G01R31/31723 ,  G01R31/31724 ,  G01R31/31725 ,  G01R31/31727 ,  G01R31/3177 ,  G01R31/318508 ,  G01R31/318536 ,  G06F17/5081

Abstract: In a first embodiment a TAP 318 of IEEE standard 1149.1 is allowed to commandeer control from a WSP 202 of IEEE standard P1500 such that the P1500 architecture, normally controlled by the WSP, is rendered controllable by the TAP. In a second embodiment (1) the TAP and WSP based architectures are merged together such that the sharing of the previously described architectural elements are possible, and (2) the TAP and WSP test interfaces are merged into a single optimized test interface that is operable to perform all operations of each separate test interface.

Abstract translation: 在第一实施例中，允许IEEE标准1149.1的TAP 318从IEEE标准P1500的WSP 202命令控制，使得通常由WSP控制的P1500架构被TAP控制。 在第二实施例（1）中，基于TAP和WSP的架构被合并在一起，使得先前描述的架构元件的共享是可能的，并且（2）TAP和WSP测试接口被合并到单个优化的测试接口中，该接口是可操作的 执行每个单独测试界面的所有操作。

公开(公告)号：US09535127B2

公开(公告)日：2017-01-03

申请号：US15243294

申请日：2016-08-22

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Lee D. Whetsel

IPC: G01R31/3177 ,  G06F11/25

CPC classification number: G01R31/31723 ,  G01R31/2851 ,  G01R31/3172 ,  G01R31/31724 ,  G01R31/3173 ,  G01R31/3177 ,  G01R31/318563 ,  G01R31/318575

Abstract: An integrated circuit includes combinational logic with flip-flops, parallel scan paths with a scan input for receiving test stimulus data to be applied to the combinational logic, combinational connections with the combinational logic for applying stimulus data to the combinational logic and receiving response data from the combinational logic, a scan output for transmitting test response data obtained from the combinational logic, and control inputs having an enable input and a select input for operating the parallel scan paths, each scan path includes flip-flops of the combinational logic that, in a test mode, are connected in series, compare circuitry indicates the result of a comparison of the received test response data and the expected data at a fail flag output, and one of the scan paths includes a scan cell having an input coupled to the fail flag output.

Abstract translation: 集成电路包括具有触发器的组合逻辑，具有用于接收要应用于组合逻辑的测试激励数据的扫描输入的并行扫描路径，与组合逻辑的组合连接，用于将刺激数据应用于组合逻辑并从 组合逻辑，用于发送从组合逻辑获得的测试响应数据的扫描输出以及具有用于操作并行扫描路径的使能输入和选择输入的控制输入，每个扫描路径包括组合逻辑的触发器， 测试模式串联连接，比较电路表示接收到的测试响应数据与故障标志输出的期望数据的比较结果，其中一个扫描路径包括具有耦合到故障的输入的扫描单元 标志输出。

公开(公告)号：US09513336B2

公开(公告)日：2016-12-06

申请号：US14978752

申请日：2015-12-22

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Lee D. Whetsel

IPC: G01R31/3177 ,  G01R31/3185

CPC classification number: G01R31/3177 ,  G01R31/31723 ,  G01R31/31724 ,  G01R31/31725 ,  G01R31/318508 ,  G01R31/318513 ,  G01R31/318555 ,  G01R31/318597

Abstract: This disclosure describes a test architecture that supports a common approach to testing individual die and dies in a 3D stack arrangement. The test architecture uses an improved TAP design to facilitate the testing of parallel test circuits within the die.

Abstract translation: 本公开描述了支持以3D堆叠布置来测试单个管芯和管芯的通用方法的测试架构。 测试架构使用改进的TAP设计来促进芯片内的并行测试电路的测试。

公开(公告)号：US20160313400A1

公开(公告)日：2016-10-27

申请号：US15203333

申请日：2016-07-06

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Lee D. Whetsel

IPC: G01R31/3183 ,  G01R31/317 ,  G01R31/3177

CPC classification number: G01R31/318335 ,  G01R31/3172 ,  G01R31/31723 ,  G01R31/31727 ,  G01R31/3177 ,  G01R31/318547 ,  G06F11/2733

Abstract: The disclosure describes novel methods and apparatuses for accessing test compression architectures (TCA) in a device using either a parallel or serial access technique. The serial access technique may be controlled by a device tester or by a JTAG controller. Further the disclosure provides an approach to access the TCA of a device when the device exists in a daisy-chain arrangement with other devices, such as in a customer's system. Additional embodiments are also provided and described in the disclosure.

公开(公告)号：US20160313397A1

公开(公告)日：2016-10-27

申请号：US15200788

申请日：2016-07-01

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Lee D. Whetsel

IPC: G01R31/3177 ,  G01R31/3185 ,  G06F1/10

CPC classification number: G01R31/3177 ,  G01R31/3172 ,  G01R31/318536 ,  G01R31/318555 ,  G01R31/318572 ,  G06F1/10

Abstract: An integrated circuit has controller circuitry having coupled to a test clock and a test mode select inputs, and having state a register clock state output, a register capture state output, and a register update state output. Register circuitry has a test data in lead input, control inputs coupled to the state outputs of the controller circuitry, and a control output. Connection circuitry has a control input connected to the control output of the register circuitry and selectively couples one of a first serial data output of first scan circuitry and a second serial data output of second scan circuitry to a test data out lead. Selection circuitry has an input connected to the serial data input lead, an input connected to a test pattern source lead, a control input coupled to the scan circuitry control output leads, and an output connected to the scan input lead.

公开(公告)号：US09435859B2

公开(公告)日：2016-09-06

申请号：US14612748

申请日：2015-02-03

Applicant: Texas Instruments Incorporated

Inventor： Lee D. Whetsel

IPC: G01R31/3177 ,  G01R31/3185

CPC classification number: G01R31/3177 ,  G01R31/31713 ,  G01R31/31723 ,  G01R31/318536 ,  H01L24/09 ,  H01L24/17 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/00

Abstract: The disclosure describes a novel method and apparatus for improving interposers that connected stacked die assemblies to system substrates. The improvement includes the addition of IEEE 1149.1 circuitry within interposers to allow simplifying interconnect testing of digital and analog signal connections between the interposer and system substrate it is attached too. The improvement also includes the additional 1149.1 controlled circuitry that allows real time monitoring of voltage supply and ground buses in the interposer. The improvement also includes the additional of 1149.1 controlled circuitry that allows real time monitoring of functional digital and analog input and output signals in the interposer. The improvement also provides the ability to selectively serially link the 1149.1 circuitry in the interposer with 1149.1 circuitry in the die of the stack.

Abstract translation: 本公开描述了一种用于改进将堆叠的管芯组件连接到系统衬底的插入件的新型方法和装置。 该改进包括在内插器中添加IEEE 1149.1电路，以便简化插入器与其所附系统基板之间的数字和模拟信号连接的互连测试。 该改进还包括额外的1149.1控制电路，允许对插入器中的电压供应和接地总线进行实时监控。 该改进还包括额外的1149.1控制电路，允许对插入器中的功能数字和模拟输入和输出信号进行实时监控。 该改进还提供了将插入器中的1149.1电路与堆叠管芯中的1149.1电路串联连接的能力。

公开(公告)号：US20160252574A1

公开(公告)日：2016-09-01

申请号：US15151035

申请日：2016-05-10

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Lee D. Whetsel

IPC: G01R31/3177 ,  G01R31/317

CPC classification number: G01R31/318335 ,  G01R31/3172 ,  G01R31/31723 ,  G01R31/31727 ,  G01R31/3177 ,  G01R31/318547 ,  G06F11/2733

Abstract: The disclosure describes novel methods and apparatuses for accessing test compression architectures (TCA) in a device using either a parallel or serial access technique. The serial access technique may be controlled by a device tester or by a JTAG controller. Further the disclosure provides an approach to access the TCA of a device when the device exists in a daisy-chain arrangement with other devices, such as in a customer's system. Additional embodiments are also provided and described in the disclosure.

公开(公告)号：US20160223613A1

公开(公告)日：2016-08-04

申请号：US15095705

申请日：2016-04-11

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Lee D. Whetsel

IPC: G01R31/3177 ,  G01R31/317

CPC classification number: G01R31/31717 ,  B82Y25/00 ,  G01R31/31701 ,  G01R31/31723 ,  G01R31/31727 ,  G01R31/3177 ,  G01R31/318536 ,  G01R31/318541 ,  G01R31/318544 ,  G01R31/318572 ,  G01R33/093

Abstract: A Propagation Test instruction, a Decay Test instruction and a Cycle Test instruction provide testing of DC and AC interconnect circuits between circuits including JTAG boundary scan cells. A few additions to the Test Access Port circuitry, including gating producing a Capture Test Strobe (CTS) signal, and the boundary scan cells are required to implement the additional instructions. The instructions are extensions of the conventional JTAG operating structure.

公开(公告)号：US20160216328A1

公开(公告)日：2016-07-28

申请号：US15089978

申请日：2016-04-04

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Lee D. Whetsel

IPC: G01R31/3177 ,  G01R31/317

CPC classification number: G01R31/3177 ,  G01R31/31724 ,  G01R31/31725 ,  G01R31/318536 ,  G01R31/318544

Abstract: The disclosure describes a novel method and apparatus for allowing response data output from the scan outputs of a circuit under test to be formatted and applied as stimulus data input to the scan inputs of the circuit under test. Also the disclosure described a novel method and apparatus for allowing the response data output from the scan outputs of a circuit under test to be formatted and used as expected data to compare against the response data output from the circuit under test. Additional embodiments are also provided and described in the disclosure.