公开(公告)号：US06934795B2

公开(公告)日：2005-08-23

申请号：US10000122

申请日：2001-10-31

Applicant: Bindiganavale S. Nataraj ,  Nilesh A. Gharia ,  Rupesh R. Roy ,  Jose P. Pereira ,  Varadarajan Srinivasan ,  Sandeep Khanna ,  Hok F. Wong

Inventor： Bindiganavale S. Nataraj ,  Nilesh A. Gharia ,  Rupesh R. Roy ,  Jose P. Pereira ,  Varadarajan Srinivasan ,  Sandeep Khanna ,  Hok F. Wong

IPC: G06F12/00 ,  G06F17/30 ,  G11C8/04 ,  G11C15/00 ,  G11C15/04 ,  H03K3/356 ,  H03K23/56 ,  G06F13/00

CPC classification number: G11C15/04 ,  G06F17/30982 ,  G11C8/04 ,  G11C15/00 ,  H03K3/356139 ,  H03K23/56

Abstract: A content addressable memory (CAM) device including a CAM array and a priority index table. The CAM array has a plurality of rows of CAM cells, each row including a plurality of row segments and being adapted to store a data word that spans a selectable number of the row segments. The priority index table is coupled to the plurality of rows of CAM cells and is adapted to store a plurality of priority numbers, each priority number being indicative of a priority of a corresponding data word stored in the CAM array.

Abstract translation: 包括CAM阵列和优先级索引表的内容可寻址存储器（CAM）装置。 CAM阵列具有多行CAM单元，每行包括多个行段，并且适于存储跨越可选数量的行段的数据字。 优先权索引表耦合到多个CAM单元行，并且适于存储多个优先级数，每个优先级数表示存储在CAM阵列中的相应数据字的优先级。

公开(公告)号：US20030028713A1

公开(公告)日：2003-02-06

申请号：US10142855

申请日：2002-05-09

Applicant: Netlogic Microsystems, Inc.

Inventor： Sandeep Khanna ,  Bindiganavale S. Nataraj ,  Varadarajan Srinivasan

IPC: G06F012/00

CPC classification number: H04L61/00 ,  G11C15/04 ,  H04L29/12009

Abstract: A method and apparatus for determining an exact match in a ternary CAM device. Each ternary CAM cell includes CAM cells for storing CAM data, local mask cells for storing prefix mask data for the corresponding CAM cells, and a mask override circuit. Each local mask cell includes a masking circuit that masks the prefix mask data or CAM data provided to the comparison circuit, or masks the comparison result from the match line of a CAM cell. The mask override circuit effectively overrides the prefix mask data stored in the local mask cell. The mask override circuit performs the override function by negating the operation of the mask circuit such that no masking operation occurs when an exact match compare or invalidate function is performed by the ternary CAM device. For example, during an exact match operation, the CAM cells compare comparand data with unmasked CAM data and provide the compare results to CAM match lines. The local mask cells also compare mask data with the stored prefix mask data and provide the results to mask match lines. If both compares result in a match, then an exact match entry is located in the ternary CAM device. The locations or indexes of the exact match entries may then be output from the CAM device. One or more of the exact match locations may also be invalidated or deleted.

公开(公告)号：US08982596B1

公开(公告)日：2015-03-17

申请号：US13301499

申请日：2011-11-21

Applicant: Varadarajan Srinivasan ,  Bindiganavale S. Nataraj ,  Sandeep Khanna

Inventor： Varadarajan Srinivasan ,  Bindiganavale S. Nataraj ,  Sandeep Khanna

IPC: G11C15/00 ,  G11C15/04 ,  G11C29/24 ,  G11C29/00

CPC classification number: G11C15/00 ,  G11C15/04 ,  G11C29/24 ,  G11C29/70 ,  G11C29/816 ,  G11C29/848

Abstract: A CAM device includes a CAM array that can implement column redundancy in which a defective column segment in a selected block can be functionally replaced by a selected column segment of the same block, and/or by a spare column segment of the same block.

Abstract translation: CAM设备包括可以实现列冗余的CAM阵列，其中所选块中的缺陷列段可以由相同块的所选列段和/或由同一块的备用列段功能地替换。

公开(公告)号：US08923384B2

公开(公告)日：2014-12-30

申请号：US11967697

申请日：2007-12-31

Applicant: Erik Schlanger ,  Rens Ross

Inventor： Erik Schlanger ,  Rens Ross

IPC: H04B1/66 ,  H04N19/61 ,  H04N19/176 ,  H04N19/436 ,  H04N19/44

CPC classification number: H04N19/14 ,  H04N19/176 ,  H04N19/436 ,  H04N19/44 ,  H04N19/61

Abstract: In one form, a video processing device (150) includes a memory (110, 130) and a plurality of staged macroblock processing engines (112, 114, 116). The memory (110, 130) is operable to store partially decoded video data decoded from a stream of encoded video data. The plurality of staged macroblock processing engines (112, 114, 116) is coupled to the memory (110, 130) and is responsive to a request to process the partially decoded video data to generate a plurality of macroblocks of decoded video data. In another form, a first a first macroblock of decoded video data having a first location (426) within a first row (408) of a video frame (400) is generated, and a second macroblock of decoded video data having a second location (424) within a second row (410) of the video frame (400) is generated during the generating of the first macroblock.

Abstract translation: 在一种形式中，视频处理设备（150）包括存储器（110,130）和多个分段宏块处理引擎（112,114,116）。 存储器（110,130）可操作以存储从编码视频数据流解码的部分解码的视频数据。 多个分级宏块处理引擎（112,114,116）耦合到存储器（110,130），并且响应于处理部分解码的视频数据以产生解码的视频数据的多个宏块的请求。 在另一形式中，生成具有在视频帧（400）的第一行（408）内的第一位置（426）的解码视频数据的第一宏块，并且具有第二位置（424）的解码视频数据的第二宏块 在第一宏块的生成期间生成在视频帧（400）的第二行（410）内。

公开(公告)号：US08917582B2

公开(公告)日：2014-12-23

申请号：US12916425

申请日：2010-10-29

Applicant: Roubik Gregorian ,  Gaurav Malhotra

Inventor： Roubik Gregorian ,  Gaurav Malhotra

IPC: H04B15/00 ,  H04B3/23

CPC classification number: H04B3/23

Abstract: A method and system are described for canceling an echo signal with an echo canceller in the analog domain. In one embodiment, a system includes an echo canceller that includes an interpolation unit, operating in a digital domain, that receives a first digital echo estimate signal from an LMS unit and generates a second digital echo estimate signal without oversampling. A digital-to-analog converter (DAC) receives the second digital echo estimate signal and generates an analog echo estimate signal without oversampling. The echo canceller prevents the DAC from adding a high frequency component to the analog echo estimate signal. A subtractor adds the analog echo signal to an incoming signal having an echo signal. The subtractor generates an analog signal with reduced echo signal in the useful frequency band of the incoming signal.

Abstract translation: 描述了用于在模拟域中用回波消除器消除回波信号的方法和系统。 在一个实施例中，系统包括回波消除器，该回波消除器包括在数字域中操作的内插单元，该内插单元从LMS单元接收第一数字回波估计信号，并产生第二数字回波估计信号而不进行过采样。 数模转换器（DAC）接收第二数字回波估计信号并产生模拟回波估计信号而不进行过采样。 回波消除器防止DAC向模拟回波估计信号添加高频分量。 减法器将模拟回波信号添加到具有回波信号的输入信号。 减法器在输入信号的有用频带中产生具有减小的回波信号的模拟信号。

公开(公告)号：US08842696B1

公开(公告)日：2014-09-23

申请号：US13165479

申请日：2011-06-21

Applicant: Ozair Usmani

Inventor： Ozair Usmani

IPC: H04J3/24 ,  H04J1/00 ,  G06F13/00

CPC classification number: G06F13/385 ,  G06F13/28 ,  G06F2213/3808

Abstract: A guaranteed rate port scheduler (GRPS) is used for serving multiple destination ports simultaneously without under-runs, even if the total bandwidth of the ports is more than the bandwidth capability of the device. Certain network protocols, such as Ethernet, do not allow “gaps” (called under-runs) to occur between bits of a packet on the wire. If a network device is transmitting packets to several such ports at the same time and the combined bandwidth of these ports is more than the device can source, under-runs begin to occur within the transmitted packets. The disclosed GRPS solves this problem by: (a) the GRPS serves only as many destination ports at a given time as can be “handled”, and (b) the GRPS fairly selects new destination ports to serve after every end-of-frame data packet transmission by effectively “de-rating” the statistical bandwidth of each destination port in proportion to the diminished capacity of the device.

Abstract translation: 即使端口的总带宽大于设备的带宽能力，保证速率端口调度器（GRPS）也可以同时服务于多个目标端口而不会运行不良。 某些网络协议（例如以太网）不允许在线路上的数据包的位之间发生“间隙”（称为运行中）。 如果网络设备同时向多个这样的端口发送数据包，并且这些端口的组合带宽大于设备可以来源，则在发送的数据包中开始发生欠运行。 所公开的GRPS通过以下方式解决了这个问题：（a）GRPS在给定时间仅服务于可以“处理”的目的地端口，并且（b）GRPS在每个帧结束后公平地选择新的目的地端口 数据包传输通过有效地“降级”每个目标端口的统计带宽与设备容量减小成比例。

公开(公告)号：US20140218994A1

公开(公告)日：2014-08-07

申请号：US14142281

申请日：2013-12-27

Applicant: NetLogic Microsystems, Inc.

Inventor： Dimitri Argyres

IPC: G11C5/14 ,  G11C15/00

CPC classification number: G11C5/14 ,  G11C15/00

Abstract: A CAM device for comparing a search key with a plurality of ternary words stored in a CAM array includes one or more population counters, a pre-compare memory, and a pre-compare circuit. The present embodiments reduce the power consumption of CAM devices during compare operations between a search key and ternary words stored in a CAM array by selectively enabling the match lines in the CAM array in response to pre-compare operations between a set of population counts corresponding to the masked search key and a set of population counts corresponding to the ternary words stored in the CAM array.

Abstract translation: 用于将搜索关键字与存储在CAM阵列中的多个三进制字进行比较的CAM装置包括一个或多个总体计数器，预比较存储器和预比较电路。 本实施例通过选择性地启用CAM阵列中的匹配线，以响应于对应于一组CAM的一组群体计数之间的预比较操作来减少CAM设备在搜索关键字和存储在CAM阵列中的三进制字之间的比较操作期间的功耗 掩蔽的搜索关键字和与存储在CAM阵列中的三元字对应的一组群体计数。

公开(公告)号：US08788732B2

公开(公告)日：2014-07-22

申请号：US13972797

申请日：2013-08-21

Applicant: NetLogic Microsystems, Inc.

Inventor： Julianne J. Zhu ,  David T. Hass

IPC: G06F13/42 ,  G06F3/00 ,  G06F13/00 ,  G06F15/76

CPC classification number: G06F13/4286 ,  G06F9/3851 ,  G06F9/3857 ,  G06F9/3867 ,  G06F12/0813 ,  H04L49/109

Abstract: An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. The data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. In one aspect of an embodiment of the invention, the messaging network connects to a high-bandwidth star-topology serial bus such as a PCI express (PCIe) interface capable of supporting multiple high-bandwidth PCIe lanes. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner.

Abstract translation: 高级处理器包括多个具有数据高速缓存和指令高速缓存的多线程处理器核心。 数据交换机互连耦合到每个处理器核并被配置为在处理器核之间传递信息。 消息传递网络耦合到每个处理器核和多个通信端口。 数据交换机互连通过其相应的数据高速缓存耦合到每个处理器核心，并且消息传递网络通过其各自的消息站耦合到每个处理器核心。 在本发明的实施例的一个方面，消息传递网络连接到能够支持多个高带宽PCIe通道的高带宽星形拓扑串行总线，例如PCI Express（PCIe）接口。 本发明的优点包括以有效和成本有效的方式在计算机系统和存储器之间提供高带宽通信的能力。

公开(公告)号：US08730704B1

公开(公告)日：2014-05-20

申请号：US13371236

申请日：2012-02-10

Applicant: Bindiganavale S. Nataraj ,  John Zimmer ,  Sandeep Khanna ,  Vinay Iyengar ,  Chetan Deshpande

Inventor： Bindiganavale S. Nataraj ,  John Zimmer ,  Sandeep Khanna ,  Vinay Iyengar ,  Chetan Deshpande

IPC: G11C15/00

CPC classification number: G11C15/04 ,  H01L27/1052

Abstract: A CAM device is disclosed that includes an array of CAM cells in which the compare circuits of groups of CAM cells are connected together using a conductive layer interposed between a polysilicon layer of the CAM device and the metal-1 layer of the CAM device. This allows the data lines (e.g., the bit lines and/or comparand lines) of the CAM array to be formed in the metal-1 layer of the CAM device, which in turn allows the match lines of the CAM array to be formed in the metal-2 layer of the CAM device. The conductive layer, which may be a silicide layer, is connected to the match line by a via extending from the conductive layer through the metal-1 layer to the metal-2 layer.

Abstract translation: 公开了一种CAM器件，其包括CAM单元阵列，其中使用介于CAM器件的多晶硅层和CAM器件的金属层之间的导电层将CAM单元组的比较电路连接在一起。 这允许CAM阵列的数据线（例如，位线和/或比较线）形成在CAM器件的金属1层中，这继而允许CAM阵列的匹配线形成在 CAM设备的金属层2层。 可以是硅化物层的导电层通过从导电层穿过金属-1层延伸到金属层2的通孔连接到匹配线。

公开(公告)号：US08700944B2

公开(公告)日：2014-04-15

申请号：US13762927

申请日：2013-02-08

Applicant: NetLogic Microsystems, Inc.

Inventor： Marc Loinaz

IPC: G06F1/00 ,  G06F1/04 ,  G06F13/00

CPC classification number: G06F12/0246 ,  G06F1/08

Abstract: Embodiments of the invention relate to programmable data register circuits and programmable clock generation circuits For example, some embodiments include a buffer circuit for receiving input data and sending output data signals along a series of signal lines with a signal strength, and a signal modulator configured to determine the signal strength based on a control input. Some embodiments include a clock generation circuit for receiving clock reference and sending output clock signals along a series of signal lines with a signal character, and a signal modulator configured to determine the signal character based on a control input.

Abstract translation: 本发明的实施例涉及可编程数据寄存器电路和可编程时钟生成电路。例如，一些实施例包括用于接收输入数据并沿着具有信号强度的一系列信号线发送输出数据信号的缓冲电路，以及配置为 根据控制输入确定信号强度。 一些实施例包括用于接收时钟参考并且沿着一系列具有信号字符的信号线发送输出时钟信号的时钟产生电路，以及被配置为基于控制输入来确定信号字符的信号调制器。