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    Intermetallic compound
    261.
    发明授权
    Intermetallic compound 有权

    公开(公告)号：US11222957B2

    公开(公告)日：2022-01-11

    申请号：US16907986

    申请日：2020-06-22

    Applicant: STMicroelectronics (Crolles 2) SAS

    Inventor： Magali Gregoire

    IPC: H01L29/45 ,  H01L21/321 ,  H01L21/285 ,  H01L21/3213 ,  H01L29/06 ,  H01L29/08 ,  H01L29/161

    Abstract: A NiPt layer with a Pt atom concentration equal to 15% plus or minus 1% is deposited on a semiconductor region (which may, for example, be a source/drain region of a MOS transistor). An anneal is then performed at a temperature of 260° C. plus or minus 20° C., for a duration in the range from 20 to 60 seconds, in order to produce, from the Nickle-Platinum (NiPt) layer and the semiconductor material of said semiconductor region, an intermetallic layer. Advantageously, the intermetallic layer possesses a structure of heteroepitaxy with the semiconductor material, and includes free Pt atoms.

    Manufacturing of cavities
    262.
    发明授权
    Manufacturing of cavities 有权

    公开(公告)号：US11171034B2

    公开(公告)日：2021-11-09

    申请号：US16707614

    申请日：2019-12-09

    Applicant: STMicroelectronics (Crolles 2) SAS

    Inventor： Pascal Gouraud ,  Delia Ristoiu

    IPC: H01L21/00 ,  H01L21/762 ,  H01L29/06

    Abstract: A substrate includes a first solid semiconductor region and a second semiconductor on insulator region. First and second cavities are simultaneously formed in the first and second regions, respectively, of the substrate using etching processes in two steps which form an upper portion and a lower portion of each cavity. The first and second cavities will each have a step at a level of an upper surface of the insulator of the second semiconductor on insulator region. A further oxidation of the first cavity produces a rounded or cut-off area for the upper portion.

    PHASE-CHANGE MEMORY CELL HAVING A COMPACT STRUCTURE
    265.
    发明申请
    PHASE-CHANGE MEMORY CELL HAVING A COMPACT STRUCTURE 有权

    公开(公告)号：US20210280779A1

    公开(公告)日：2021-09-09

    申请号：US17328917

    申请日：2021-05-24

    Applicant: STMICROELECTRONICS (CROLLES 2) SAS ,  STMICROELECTRONICS (ROUSSET) SAS

    Inventor： Philippe BOIVIN ,  Simon JEANNOT

    IPC: H01L45/00 ,  H01L27/24

    Abstract: A memory cell includes a selection transistor having a control gate and a first conduction terminal connected to a variable-resistance element. The memory cell is formed in a wafer comprising a semiconductor substrate covered with a first insulating layer, the insulating layer being covered with an active layer made of a semiconductor. The gate is formed on the active layer and has a lateral flank covered with a second insulating layer. The variable-resistance element includes a first layer covering a lateral flank of the active layer in a trench formed through the active layer along the lateral flank of the gate and reaching the first insulating layer, and a second layer made of a variable-resistance material.

    CO-INTEGRATED VERTICALLY STRUCTURED CAPACITIVE ELEMENT AND FABRICATION PROCESS
    268.
    发明申请
    CO-INTEGRATED VERTICALLY STRUCTURED CAPACITIVE ELEMENT AND FABRICATION PROCESS 有权

    公开(公告)号：US20210225757A1

    公开(公告)日：2021-07-22

    申请号：US17226324

    申请日：2021-04-09

    Applicant: STMicroelectronics (Rousset) SAS ,  STMicroelectronics (Crolles 2) SAS

    Inventor： Abderrezak MARZAKI ,  Arnaud REGNIER ,  Stephan NIEL

    IPC: H01L23/522 ,  H01L49/02 ,  H01L27/11524

    Abstract: First and second wells are formed in a semiconductor substrate. First and second trenches in the first second wells, respectively, each extend vertically and include a central conductor insulated by a first insulating layer. A second insulating layer is formed on a top surface of the semiconductor substrate. The second insulating layer is selectively thinned over the second trench. A polysilicon layer is deposited on the second insulating layer and then lithographically patterned to form: a first polysilicon portion over the first well that is electrically connected to the central conductor of the first trench to form a first capacitor plate, a second capacitor plate formed by the first well; and a second polysilicon portion over the second well forming a floating gate electrode of a floating gate transistor of a memory cell having an access transistor whose control gate is formed by the central conductor of the second trench.

    IMAGE SENSOR INTENDED TO BE ILLUMINATED VIA A BACK SIDE, AND CORRESPONDING METHOD FOR ACQUIRING A LIGHT FLUX
    269.
    发明申请
    IMAGE SENSOR INTENDED TO BE ILLUMINATED VIA A BACK SIDE, AND CORRESPONDING METHOD FOR ACQUIRING A LIGHT FLUX 有权

    公开(公告)号：US20210193708A1

    公开(公告)日：2021-06-24

    申请号：US17122394

    申请日：2020-12-15

    Applicant: STMicroelectronics (Crolles 2) SAS

    Inventor： Francois ROY

    IPC: H01L27/146

    Abstract: A back side illuminated image sensor includes a pixel formed by three doped photosensitive regions that are superposed vertically in a semiconductor substrate. Each photosensitive region is laterally framed by a respective vertical annular gate. The vertical annular gates are biased by a control circuit during an integration phase so as to generate an electrostatic potential comprising potential wells in the central portion of the volume of each doped photosensitive region and a potential barrier at each interface between two neighboring doped photosensitive regions.

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