公开(公告)号：US06551885B1

公开(公告)日：2003-04-22

申请号：US09779986

申请日：2001-02-09

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L21336

CPC classification number: H01L29/66772 ,  H01L29/458 ,  H01L29/66545 ,  H01L29/78618

Abstract: A method of manufacturing an integrated circuit utilizes a thin film substrate and a high-k gate dielectric. The method includes providing a mask structure on a top surface of the thin film, depositing a semiconductor material above the top surface of the thin film and the mask structure, removing the semiconductor material to a level below the top surface of the mask structure, siliciding the semiconductor material, and providing a gate structure in an aperture formed by removing the mask structure. The transistor can be a fully depleted transistor having material for siliciding source and drain regions.

Abstract translation: 集成电路的制造方法利用薄膜基板和高k栅极电介质。 该方法包括在薄膜的顶表面上提供掩模结构，在半导体材料的上表面和掩模结构之上沉积半导体材料，将半导体材料去除到掩模结构的顶表面以下的水平，硅化 半导体材料，并且通过去除掩模结构形成的孔中提供栅极结构。 晶体管可以是具有用于硅化源极和漏极区域的材料的完全耗尽的晶体管。

公开(公告)号：US06475890B1

公开(公告)日：2002-11-05

申请号：US09789939

申请日：2001-02-12

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L2144

CPC classification number: H01L29/7853 ,  H01L29/42384 ,  H01L29/66795

Abstract: For fabricating a field effect transistor on a semiconductor substrate in SOI (semiconductor on insulator) technology, a pillar of semiconductor material is formed on a layer of buried insulating material. The pillar has a top surface and first and second side surfaces, and the pillar has a width, a length, and a height. A masking structure is formed on a center portion of the top surface of the pillar along the length of the pillar. A top portion of the height of the pillar is etched from exposed surfaces of the top surface of the pillar down to a bottom portion of the height of the pillar to form an upside down T-shape for the pillar. A gate dielectric material is deposited on any exposed surface of the semiconductor material of the pillar for a gate length along the length of the pillar. A gate electrode material is deposited on the gate dielectric material to surround the pillar for the gate length of the pillar. A drain and source dopant is implanted into exposed regions of the pillar to form a drain of the field effect transistor on a first side of the gate electrode material along the length of the pillar and to form a source of the field effect transistor on a second side of the gate electrode material along the length of the pillar. In this manner, for a given height and width of the semiconductor pillar, any point of a cross-section of such a pillar is more closely located to the gate bias applied at a surface of such a pillar to maximize effective drive current while minimizing undesired short channel effects of the field effect transistor.

Abstract translation: 为了在SOI（绝缘体上半导体）技术的半导体衬底上制造场效应晶体管，在掩埋绝缘材料层上形成半导体材料柱。 支柱具有顶表面和第一和第二侧表面，并且柱具有宽度，长度和高度。 掩模结构沿着柱的长度形成在柱的顶表面的中心部分上。 柱的高度的顶部从柱的顶表面的暴露表面蚀刻到柱的高度的底部，以形成柱的上下颠倒的T形。 栅极电介质材料沉积在沿着柱的长度的栅极长度的柱的半导体材料的任何暴露的表面上。 栅极电极材料沉积在栅极电介质材料上以围绕柱的栅极长度的柱。 将漏极和源极掺杂剂注入到柱的暴露区域中，以在栅极电极材料的沿着该柱的长度的第一侧上形成场效应晶体管的漏极，并在第二个栅极晶体管的一端形成一个源极 沿着柱的长度的栅电极材料的侧面。 以这种方式，对于给定的半导体柱的高度和宽度，这种柱的横截面的任何点更接近于施加在这种柱的表面处的栅极偏置，以最大化有效的驱动电流，同时最小化不期望的 场效应晶体管的短通道效应。

公开(公告)号：US06459141B2

公开(公告)日：2002-10-01

申请号：US09495075

申请日：2000-01-31

Applicant: Bin Yu ,  Che-Hoo Ng

Inventor： Bin Yu ,  Che-Hoo Ng

IPC: H01L2904

CPC classification number: H01L21/26506 ,  H01L21/26513 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/092 ,  H01L29/1079

Abstract: The invention provides an improved well structure for electrically separating n-channel and p-channel MOSFETs. The invention first forms a shallow well in a substrate. A buried amorphous layer is then formed below the shallow well. A deep well is then formed below the buried amorphous layer. The substrate is then subjected to a rapid thermal anneal to recrystallize the buried amorphous layer. The well structure is formed by the shallow well and the deep well. A conventional semiconductor device may then be formed above the well structure. The buried amorphous layer suppresses the channeling effect during the forming of the deep well without requiring a tilt angle.

Abstract translation: 本发明提供了用于电分离n沟道和p沟道MOSFET的改进的阱结构。 本发明首先在基底中形成浅井。 然后在浅井下面形成掩埋非晶层。 然后在埋入的非晶层下方形成深井。 然后对衬底进行快速热退火以使埋入的非晶层重结晶。 井结构由浅井和深井组成。 然后可以在阱结构之上形成常规的半导体器件。 掩埋非晶层在形成深井期间抑制沟道效应，而不需要倾斜角。

公开(公告)号：US06441433B1

公开(公告)日：2002-08-27

申请号：US09824412

申请日：2001-04-02

Applicant: William G. En ,  Srinath Krishnan ,  Dong-Hyuk Ju ,  Bin Yu

Inventor： William G. En ,  Srinath Krishnan ,  Dong-Hyuk Ju ,  Bin Yu

IPC: H01L3113

CPC classification number: H01L29/66507 ,  H01L21/28518 ,  H01L29/41733 ,  H01L29/458 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66772 ,  H01L29/78603 ,  H01L29/78621 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A transistor device formed on a semiconductor-on-insulator (SOI) substrate with a buried oxide (BOX) layer disposed thereon and an active layer disposed on the BOX layer having active regions defined by isolation trenches. The device includes a gate defining a channel interposed between a source and a drain formed within the active region of the SOI substrate. Further, the device includes a multi-thickness silicide layer formed on the main source and drain regions and source and drain extension regions wherein a portion of the multi-thickness silicide layer which is formed on the source and drain extension regions is thinner than a portion of the silicide layer which is formed on the main source and drain regions. The device further includes a second thin silicide layer formed on a polysilicon electrode of the gate.

Abstract translation: 一种在绝缘体上半导体（SOI）衬底上形成的埋置氧化物（BOX）层的晶体管器件，以及设置在具有由隔离沟槽限定的有源区域的BOX层上的有源层。 该器件包括限定插入在SOI衬底的有源区域内形成的源极和漏极之间的沟道的栅极。 此外，器件包括形成在主源极和漏极区域以及源极和漏极延伸区域上的多层硅化物层，其中形成在源极和漏极延伸区域上的多层硅化物层的一部分比部分 形成在主源极和漏极区上的硅化物层。 该器件还包括形成在栅极的多晶硅电极上的第二薄硅化物层。

公开(公告)号：US06432784B1

公开(公告)日：2002-08-13

申请号：US09804162

申请日：2001-03-12

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L21336

CPC classification number: H01L29/66477 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/78

Abstract: The disclosure includes an exemplary embodiment which relates to a method of forming L-shaped spacers in an integrated circuit. This method can include providing a gate structure over a semiconductor substrate, depositing a spacer material adjacent lateral sides of the gate structure, forming dummy oxide spacer structures over the spacer material where the dummy oxide spacer structures are shaped to selectively cover an L-shaped portion of the spacer material, removing portions of the spacer material not covered by the dummy oxide spacer structures, and removing the dummy oxide spacer structures.

Abstract translation: 本公开包括一个示例性实施例，其涉及在集成电路中形成L形间隔物的方法。 该方法可以包括在半导体衬底上提供栅极结构，在栅极结构的侧面附近沉积间隔物材料，在间隔物材料上形成虚拟氧化物间隔物结构，其中虚拟氧化物间隔物结构被成形为选择性地覆盖L形部分 去除未被虚拟氧化物间隔物结构覆盖的间隔物材料的部分，以及去除虚拟氧化物间隔物结构。

公开(公告)号：US06420218B1

公开(公告)日：2002-07-16

申请号：US09559368

申请日：2000-04-24

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L21335

CPC classification number: H01L29/78696 ,  H01L29/458 ,  H01L29/66772 ,  H01L29/78618

Abstract: An ultra-large-scale integrated (ULSI) circuit includes MOSFETs on an SOI substrate. The MOSFETs include recessed source and drain regions. The recessed source and drain regions are formed utilizing an amorphous semiconductor layer. The recessed source and drain regions allow sufficient material for silicidation and yet allow an ultra thin channel region to be utilized. The channel region is above an insulative island.

Abstract translation: 超大规模集成（ULSI）电路包括SOI衬底上的MOSFET。 MOSFET包括凹陷的源极和漏极区域。 凹陷的源极和漏极区域利用非晶半导体层形成。 凹陷的源极和漏极区域允许足够的硅化物材料，并允许利用超薄沟道区域。 通道区域在绝缘岛之上。

公开(公告)号：US06413829B1

公开(公告)日：2002-07-02

申请号：US09872719

申请日：2001-06-01

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L21331

CPC classification number: H01L29/41733 ,  H01L29/458 ,  H01L29/47

Abstract: For forming a field effect transistor on a buried insulating material in SOI (semiconductor on insulator) technology, a gate dielectric and a gate electrode are formed on the semiconductor material, and spacers are formed on sidewalls of the gate electrode and the gate dielectric. The spacers cover portions of the semiconductor material. A dopant is implanted into exposed regions of the semiconductor material to form a drain doped region and a source doped region. A portion of the drain doped region and a portion of the source doped region extend under the spacers. A drain contact silicide is formed with an exposed portion of the drain doped region, and a source contact silicide is formed with an exposed portion of the source doped region. The spacers are removed to expose the portions of the semiconductor material including a portion of the drain doped region and a portion of the source doped region. A drain extension silicide is formed with a first exposed portion of the semiconductor material disposed between the drain contact silicide and the gate dielectric, and with the portion of the drain doped region disposed by the drain contact silicide. A source extension silicide is formed with a second exposed portion of the semiconductor material disposed between the source contact silicide and the gate dielectric, and with the source doped region disposed by the source contact silicide. The drain and source extension silicides are formed to be thinner than the drain and source contact silicides.

Abstract translation: 为了在SOI（绝缘体上半导体）技术的掩埋绝缘材料上形成场效应晶体管，在半导体材料上形成栅极电介质和栅电极，并且在栅电极和栅极电介质的侧壁上形成间隔物。 间隔件覆盖半导体材料的部分。 将掺杂剂注入到半导体材料的暴露区域中以形成漏极掺杂区域和源极掺杂区域。 漏极掺杂区域的一部分和源极掺杂区域的一部分在间隔物的下方延伸。 漏极接触硅化物形成有漏极掺杂区域的暴露部分，源极接触硅化物形成有源极掺杂区域的暴露部分。 去除间隔物以暴露包括漏极掺杂区域的一部分和源极掺杂区域的一部分的半导体材料的部分。 漏极延伸硅化物形成有设置在漏极接触硅化物和栅极电介质之间的半导体材料的第一暴露部分，并且漏极掺杂区域的部分由漏极接触硅化物设置。 源极延伸硅化物形成有设置在源极接触硅化物和栅极电介质之间的半导体材料的第二暴露部分，并且源极掺杂区域由源极接触硅化物设置。 漏极和源极延伸硅化物形成为比漏极和源极接触硅化物薄。

公开(公告)号：US06395589B1

公开(公告)日：2002-05-28

申请号：US09781783

申请日：2001-02-12

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L21338

CPC classification number: H01L29/66772 ,  H01L29/41733 ,  H01L29/4908

Abstract: For fabricating a field effect transistor on a semiconductor substrate in SOI (semiconductor on insulator) technology, an insulating block comprised of insulating material is formed on a thin semiconductor island comprised of semiconductor material. Semiconductor material is further grown from sidewalls of the semiconductor island to extend up along sidewalls of the insulating block to form a raised drain structure on a first side of the insulating block and the semiconductor island and to form a raised source structure on a second side of the insulating block and the semiconductor island. A drain and source dopant is implanted into the raised drain and source structures. A thermal anneal is performed to activate the drain and source dopant within the raised drain and source structures and such that the drain and source dopant extends partially into the semiconductor island. Drain and source silicides are formed within the raised drain and source structures. The insulating block is etched away to form a block opening. A gate dielectric comprised of a high dielectric constant material is deposited at a bottom wall of the block opening after the thermal anneal and after formation of the drain and source silicides. The block opening is filled with a conductive material to form a gate structure disposed over the semiconductor island. The portion of the semiconductor island disposed under the gate structure forms a channel region that is fully depleted during operation of the field effect transistor. In this manner, the gate dielectric comprised of the high dielectric constant material is formed after any process step using a relatively high temperature of greater than about 750° Celsius to preserve the integrity of the gate dielectric comprised of a high-K dielectric material.

Abstract translation: 为了在SOI（绝缘体上半导体）技术的半导体衬底上制造场效应晶体管，在由半导体材料构成的薄半导体岛上形成由绝缘材料组成的绝缘块。 半导体材料进一步从半导体岛的侧壁生长，沿着绝缘块的侧壁向上延伸，以在绝缘块和半导体岛的第一侧上形成升高的漏极结构，并在第二侧上形成升高的源极结构 绝缘块和半导体岛。 漏极和源极掺杂剂被注入到升高的漏极和源极结构中。 执行热退火以激活凸起的漏极和源极结构内的漏极和源极掺杂剂，并且使得漏极和源极掺杂物部分地延伸到半导体岛中。 排水和源硅化物形成在升高的漏极和源极结构内。 绝缘块被蚀刻掉以形成块开口。 由高介电常数材料构成的栅极电介质在热退火之后和在形成漏极和源极硅化物之后沉积在块开口的底壁处。 块开口填充有导电材料以形成设置在半导体岛上的栅极结构。 设置在栅极结构下面的半导体岛的部分形成在场效应晶体管的工作期间完全耗尽的沟道区。 以这种方式，由高介电常数材料组成的栅极电介质是在使用大于约750℃的较高温度的任何工艺步骤之后形成的，以保持由高K电介质材料构成的栅极电介质的完整性。

公开(公告)号：US06391695B1

公开(公告)日：2002-05-21

申请号：US09633312

申请日：2000-08-07

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L2100

CPC classification number: H01L29/66772 ,  H01L29/78639 ,  H01L29/78648

Abstract: A method for forming a double-gate SOI MOS transistor with a back gate formed by a laser thermal process is described. In this method, a back gate is formed in a semiconductor substrate and is subsequently amorphized by implanting an amorphization species such as germanium, silicon, and xenon. The amorphous back gate region is melted using a laser annealing process and subsequently recrystallized to form the back gate.

Abstract translation: 描述了通过激光热处理形成的具有背栅的双栅极SOI MOS晶体管的形成方法。 在该方法中，在半导体衬底中形成背栅，并且随后通过注入非晶化物质如锗，硅和氙来非晶化。 使用激光退火工艺熔化无定形背栅区，随后重结晶形成背栅。

公开(公告)号：US06380043B1

公开(公告)日：2002-04-30

申请号：US09781357

申请日：2001-02-12

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L21336

CPC classification number: H01L29/517 ,  H01L21/28167 ,  H01L29/41783 ,  H01L29/66636 ,  H01L29/7834

Abstract: For fabricating a field effect transistor, a gate structure is formed on a gate dielectric on an active device area of a semiconductor substrate. An amorphization dopant and an extension dopant are implanted into exposed regions of the active device area to form drain and source extension junctions extending down to an extension depth within the semiconductor substrate. First and second spacers are formed at sidewalls of the gate structure. Any exposed regions of the active device area of the semiconductor substrate are etched down beyond the extension depth. The drain and source extension junctions remain disposed under the first and second spacers. A layer of doped amorphous semiconductor material is deposited to cover the structures on the semiconductor substrate and is doped with a contact dopant in an in-situ deposition process using a temperature of less than about 500° Celsius. The amorphous semiconductor material is polished down until the top surfaces of the gate structure and the first and second spacers are level with a top surface of the amorphous semiconductor material. The amorphous semiconductor material remaining to the first sidewall of the gate structure forms an elevated drain contact structure, and the amorphous semiconductor material remaining to the second sidewall of the gate structure forms an elevated source contact structure. A thermal anneal is performed using a temperature less than about 600° Celsius to activate the dopants within the drain and source extension junctions and within the drain and source contact structures. Such low temperatures preserve the gate dielectric comprised of a high-K dielectric material.

Abstract translation: 为了制造场效应晶体管，在半导体衬底的有源器件区域上的栅极电介质上形成栅极结构。 将非晶化掺杂剂和延伸掺杂剂注入到有源器件区域的暴露区域中，以形成向下延伸到半导体衬底内的延伸深度的漏极和源极延伸结。 第一和第二间隔件形成在栅极结构的侧壁处。 将半导体衬底的有源器件区域的任何暴露区域向下蚀刻超过延伸深度。 漏极和源极延伸接头保持布置在第一和第二间隔物下方。 沉积一层掺杂的非晶半导体材料以覆盖半导体衬底上的结构，并使用低于约500℃的温度在原位沉积工艺中掺杂接触掺杂剂。 将非晶半导体材料抛光直到栅极结构的顶表面和第一和第二间隔物与非晶半导体材料的顶表面平齐。 残留在栅极结构的第一侧壁上的非晶半导体材料形成升高的漏极接​​触结构，并且留在栅极结构的第二侧壁上的非晶半导体材料形成升高的源极接触结构。 使用低于约600℃的温度进行热退火，以激活漏极和源极延伸结内部以及漏极和源极接触结构内的掺杂剂。 这种低温保存由高K电介质材料构成的栅极电介质。