公开(公告)号：US20200083378A1

公开(公告)日：2020-03-12

申请号：US16682327

申请日：2019-11-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Cheng Chang ,  Chih-Han Lin

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/51 ,  H01L29/06 ,  H01L21/311

Abstract: A semiconductor device includes a substrate, at least two gate spacers, and a gate stack. The substrate has at least one semiconductor fin. The gate spacers are disposed on the substrate. At least one of the gate spacers has a sidewall facing to another of the gate spacers. The gate stack is disposed between the gate spacers. The gate stack includes a high-κ dielectric layer and a gate electrode. The high-κ dielectric layer is disposed on the substrate and covers at least a portion of the semiconductor fin while leaving the sidewall of said at least one gate spacer uncovered. The gate electrode is disposed on the high-κ dielectric layer.

公开(公告)号：US10541204B2

公开(公告)日：2020-01-21

申请号：US14983412

申请日：2015-12-29

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Che-Cheng Chang ,  Chih-Han Lin

IPC: H01L23/00 ,  H01L23/528 ,  H01L21/768 ,  H01L23/485 ,  H01L23/522

Abstract: An interconnection structure includes a non-insulator structure, a dielectric structure, and a conductive structure. The dielectric structure is present on the non-insulator structure. The dielectric structure has a trench opening and a via opening therein. The trench opening has a bottom surface and at least one recess in the bottom surface. The via opening is present between the trench opening and the non-insulator structure. The conductive structure is present in the trench opening and the via opening and electrically connected to the non-insulator structure. The conductive structure is at least separated from the bottom of the recess.

公开(公告)号：US20200013881A1

公开(公告)日：2020-01-09

申请号：US16550743

申请日：2019-08-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Cheng Chang ,  Chih-Han Lin ,  Wei-Chiang Hung ,  Wei-Hao Huang

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/165 ,  H01L29/417 ,  H01L21/762 ,  H01L21/02 ,  H01L21/306 ,  H01L21/324

Abstract: Examples of an integrated circuit and a method for forming the integrated circuit are provided herein. In some examples, a method includes receiving a substrate that includes: a plurality of fins extending above a remainder of the substrate; a first region that includes a first fence region that contains a first subset of the plurality of fins; and a second region that includes a second fence region that contains a second subset of the plurality of fins. The first region has a first performance characteristic, and the second region has a second performance characteristic that is different from the first. Based on the first performance characteristic, the first subset of the plurality of fins is recessed to a first height, and based on the second performance characteristic, the second subset of the plurality of fins is recessed to a second height that is less than the first height.

公开(公告)号：US20200006148A1

公开(公告)日：2020-01-02

申请号：US16161833

申请日：2018-10-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chang-Yin Chen ,  Che-Cheng Chang ,  Chih-Han Lin

IPC: H01L21/8238 ,  H01L29/66 ,  H01L29/51 ,  H01L29/49 ,  H01L27/092 ,  H01L29/10 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/308

Abstract: A method includes providing a structure having a first region and a second region, the first region including a first channel region, the second region including a second channel region; forming a gate stack layer over the first and second regions; patterning the gate stack layer, thereby forming a first gate stack over the first channel region and a second gate stack over the second channel region; and laterally etching bottom portions of the first and second gate stacks by applying different etchant concentrations to the first and second regions simultaneously, thereby forming notches at the bottom portions of the first and second gate stacks.

公开(公告)号：US10515793B2

公开(公告)日：2019-12-24

申请号：US15921624

申请日：2018-03-14

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Che-Cheng Chang ,  Chih-Han Lin ,  Horng-Huei Tseng

IPC: H01L21/02 ,  H01L29/78 ,  H01L29/66 ,  H01L21/306 ,  H01L29/06

Abstract: A device includes a fin structure, a dielectric layer, a gate a spacer, and an epitaxy structure. The dielectric layer is over the fin structure. The gate is over the dielectric layer. The spacer is on a sidewall of the gate. The spacer has a thickness along a direction parallel to a longitudinal axis of the fin structure, and a distance along the direction from an outer sidewall of the spacer to an end surface of the fin structure is greater than the thickness of the spacer. The epitaxy structure is in contact with the fin structure.

公开(公告)号：US10510890B2

公开(公告)日：2019-12-17

申请号：US16214156

申请日：2018-12-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Cheng Chang ,  Chih-Han Lin

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/66

Abstract: A fin-type field effect transistor comprising a substrate, a plurality of insulators, at least one gate stack and strained material portions is described. The substrate has a plurality of fins thereon and the fin comprises a stop layer embedded therein. The plurality of insulators is disposed on the substrate and between the plurality of fins. The at least one gate stack is disposed over the plurality of fins and on the plurality of insulators. The strained material portions are disposed on two opposite sides of the at least one gate stack.

公开(公告)号：US10510755B2

公开(公告)日：2019-12-17

申请号：US16041996

申请日：2018-07-23

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Che-Cheng Chang ,  Chih-Han Lin ,  Horng-Huei Tseng

IPC: H01L27/092 ,  H01L29/78 ,  H01L27/088 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66

Abstract: A semiconductor device includes a semiconductor substrate and at least one gate stack. The gate stack is present on the semiconductor substrate, and the gate stack includes at least one work function conductor and a filling conductor. The work function conductor has a recess therein. The filling conductor includes a plug portion and a cap portion. The plug portion is present in the recess of the work function conductor. The cap portion caps the work function conductor.

公开(公告)号：US10483398B2

公开(公告)日：2019-11-19

申请号：US16042164

申请日：2018-07-23

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Che-Cheng Chang ,  Chih-Han Lin

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/66 ,  H01L29/417 ,  H01L21/28

Abstract: A semiconductor device is provided. The semiconductor device includes a gate stack over a semiconductor substrate. The semiconductor device also includes a protection element over the gate stack, and a top and a bottom of the protection element have different widths. The semiconductor device further includes a spacer over a side surface of the protection element and a sidewall of the gate stack. In addition, the semiconductor device includes a conductive contact electrically connected to a conductive feature over the semiconductor substrate.

公开(公告)号：US20190148287A1

公开(公告)日：2019-05-16

申请号：US15964276

申请日：2018-04-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Cheng Chang ,  Chih-Han Lin

IPC: H01L23/522 ,  H01L23/532 ,  H01L23/528 ,  H01L21/768 ,  H01L21/311 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/288 ,  H01L21/027

Abstract: A semiconductor device includes a substrate having a channel region; a gate stack over the channel region; a seal spacer covering a sidewall of the gate stack, the seal spacer including silicon nitride; a gate spacer covering a sidewall of the seal spacer, the gate spacer including silicon oxide, the gate spacer having a first vertical portion and a first horizontal portion; and a first dielectric layer covering a sidewall of the gate spacer, the first dielectric layer including silicon nitride.

公开(公告)号：US20190148214A1

公开(公告)日：2019-05-16

申请号：US15847307

申请日：2017-12-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Cheng Chang ,  Chih-Han Lin

IPC: H01L21/764 ,  H01L27/092 ,  H01L29/06 ,  H01L29/66 ,  H01L21/8238

CPC classification number: H01L21/764 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/66545

Abstract: A semiconductor device includes a first gate structure disposed over a substrate. The first gate structure extends in a first direction. A second gate structure is disposed over the substrate. The second gate structure extends in the first direction. A dielectric material is disposed between the first gate structure and the second gate structure. An air gap is disposed within the dielectric material.