公开(公告)号：US09312174B2

公开(公告)日：2016-04-12

申请号：US14109920

申请日：2013-12-17

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Cheng Tung

IPC: H01L21/768 ,  H01L21/28 ,  H01L21/74

CPC classification number: H01L21/76897 ,  H01L21/0337 ,  H01L21/28 ,  H01L21/31144 ,  H01L21/743 ,  H01L21/768 ,  H01L21/76816 ,  H01L21/76831

Abstract: A method for manufacturing contact plugs for semiconductor devices includes the following steps. A substrate is provided. The substrate includes a plurality of transistor and a first dielectric layer filling spaces between the transistors formed thereon. The transistors respectively include a gate and a source/drain. A patterned sacrificial layer is formed on the first dielectric layer. The patterned sacrificial layer includes a plurality of first openings corresponding to the gates of the transistors. A second dielectric layer filling up the first openings in the patterned sacrificial layer is formed and followed by removing the sacrificial layer to form a plurality of second openings in the second dielectric layer. The second openings are formed correspondingly to the sources/drains of the transistors. An etching process is performed to etch the first dielectric layer through the second openings to form a plurality of first contact holes exposing the sources/drains of the transistors.

Abstract translation: 一种用于制造用于半导体器件的接触插塞的方法包括以下步骤。 提供基板。 衬底包括多个晶体管和在其上形成的晶体管之间填充空间的第一介电层。 晶体管分别包括栅极和源极/漏极。 图案化的牺牲层形成在第一介电层上。 图案化牺牲层包括对应于晶体管的栅极的多个第一开口。 形成填充图案化牺牲层中的第一开口的第二电介质层，然后去除牺牲层，以在第二介电层中形成多个第二开口。 第二开口对应于晶体管的源极/漏极形成。 执行蚀刻工艺以通过第二开口蚀刻第一介电层，以形成暴露晶体管的源极/漏极的多个第一接触孔。

公开(公告)号：US20160079173A1

公开(公告)日：2016-03-17

申请号：US14489461

申请日：2014-09-17

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Cheng Tung

IPC: H01L23/532 ,  H01L21/02 ,  H01L21/033 ,  H01L23/528 ,  H01L21/768

CPC classification number: H01L23/53238 ,  H01L21/31144 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/76885 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming an ultra low-k (ULK) dielectric layer on the substrate; forming a hard mask on the ULK dielectric layer; forming an opening in the hard mask and the ULK dielectric layer; forming a conductive layer in the opening and on the hard mask; planarizing the conductive layer; and removing the hard mask to expose the ULK dielectric layer so that the top surface of the ULK dielectric layer is lower than the top surface of the conductive layer.

Abstract translation: 公开了半导体器件的制造方法。 该方法包括以下步骤：提供衬底; 在所述衬底上形成超低k（ULK）介质层; 在ULK介电层上形成硬掩模; 在硬掩模和ULK介电层中形成开口; 在开口和硬掩模上形成导电层; 平面化导电层; 并且去除硬掩模以暴露ULK电介质层，使得ULK电介质层的顶表面低于导电层的顶表面。

公开(公告)号：US20150193573A1

公开(公告)日：2015-07-09

申请号：US14151785

申请日：2014-01-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Cheng Tung

IPC: G06F17/50

CPC classification number: G03F1/36 ,  G03F7/70441 ,  G03F7/70466

Abstract: A method for generating a layout pattern of integrated circuit (IC) is provided. First, feature patterns are provided to a computer system and dummy pad patterns are generated in a space among the feature patterns. The layout pattern is then split into first feature patterns and second feature patterns. The dimensions of the first feature patterns are less than the dimensions of the second feature patterns. Afterwards, the dummy pad patterns are combined with the second features pattern to form a combined pattern. Then, mandrel patterns are generated in a space between the first feature patterns and the geometric patterns are generated according to the positions of the first feature patterns. Finally, the combined pattern, the mandrel patterns, and the geometric patterns are respectively outputted to form a first, a second, and a third photomasks.

Abstract translation: 提供了一种用于生成集成电路（IC）的布局图案的方法。 首先，将特征图案提供给计算机系统，并且在特征图案之间的空间中生成虚拟垫图案。 然后将布局图案分割成第一特征图案和第二特征图案。 第一特征图案的尺寸小于第二特征图案的尺寸。 之后，将虚拟焊盘图形与第二特征图案组合以形成组合图案。 然后，在第一特征图案之间的空间中产生心轴图案，并且根据第一特征图案的位置生成几何图案。 最后，分别输出组合图案，心轴图案和几何图案以形成第一，第二和第三光掩模。

公开(公告)号：US20150170966A1

公开(公告)日：2015-06-18

申请号：US14109920

申请日：2013-12-17

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Cheng Tung

IPC: H01L21/768

CPC classification number: H01L21/76897 ,  H01L21/0337 ,  H01L21/28 ,  H01L21/31144 ,  H01L21/743 ,  H01L21/768 ,  H01L21/76816 ,  H01L21/76831

Abstract: A method for manufacturing contact plugs for semiconductor devices includes the following steps. A substrate is provided. The substrate includes a plurality of transistor and a first dielectric layer filling spaces between the transistors formed thereon. The transistors respectively include a gate and a source/drain. A patterned sacrificial layer is formed on the first dielectric layer. The patterned sacrificial layer includes a plurality of first openings corresponding to the gates of the transistors. A second dielectric layer filling up the first openings in the patterned sacrificial layer is formed and followed by removing the sacrificial layer to form a plurality of second openings in the second dielectric layer. The second openings are formed correspondingly to the sources/drains of the transistors. An etching process is performed to etch the first dielectric layer through the second openings to form a plurality of first contact holes exposing the sources/drains of the transistors.

Abstract translation: 一种用于制造用于半导体器件的接触插塞的方法包括以下步骤。 提供基板。 衬底包括多个晶体管和在其上形成的晶体管之间填充空间的第一介电层。 晶体管分别包括栅极和源极/漏极。 图案化的牺牲层形成在第一介电层上。 图案化牺牲层包括对应于晶体管的栅极的多个第一开口。 形成填充图案化牺牲层中的第一开口的第二电介质层，然后去除牺牲层，以在第二介电层中形成多个第二开口。 第二开口对应于晶体管的源极/漏极形成。 执行蚀刻工艺以通过第二开口蚀刻第一介电层，以形成暴露晶体管的源极/漏极的多个第一接触孔。

公开(公告)号：US09032340B2

公开(公告)日：2015-05-12

申请号：US14215635

申请日：2014-03-17

Applicant: United Microelectronics Corp.

Inventor： Yu-Cheng Tung

IPC: G06F17/50 ,  G03F1/70

CPC classification number: G06F17/5081 ,  G03F1/70 ,  G06F17/5045 ,  G06F17/5072

Abstract: A layout decomposition method and a method for manufacturing a semiconductor device applying the same are provided. According to the layout decomposition method, a design layout is received by the logic processer of a computing system. A design rule for layout decomposition is then identified by the logic processer, including identifying the loose areas (areas with loosely distributed features) and dense areas (areas with densely distributed features) on a substrate, and identifying first areas with odd-numbered features and second areas with even-numbered features on the substrate. Next, a first mask with a first pattern and a second mask with a second pattern are generated corresponding to results of design rule identification by the computing system.

Abstract translation: 提供了布局分解方法和制造应用其的半导体器件的方法。 根据布局分解方法，计算系统的逻辑处理器接收到设计布局。 然后由逻辑处理器识别布局分解的设计规则，包括识别衬底上松散区域（具有松散分布特征的区域）和密集区域（具有密集分布特征的区域），以及识别具有奇数特征的第一区域，以及 在基板上具有偶数特征的第二区域。 接下来，对应于计算系统的设计规则识别的结果，生成具有第一图案的第一掩模和具有第二图案的第二掩模。

公开(公告)号：US20140134543A1

公开(公告)日：2014-05-15

申请号：US13676185

申请日：2012-11-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Cheng Tung

IPC: G06F17/50 ,  G03F7/20

CPC classification number: G06F17/5081 ,  G03F1/70 ,  G06F17/5045 ,  G06F17/5072

Abstract: A layout decomposition method and a method for manufacturing a semiconductor device applying the same are provided. According to the layout decomposition method, a design layout is received by the logic processer of a computing system. A design rule for layout decomposition is then identified by the logic processer, including identifying the loose areas (areas with loosely distributed features) and dense areas (areas with densely distributed features) on a substrate, and identifying first areas with odd-numbered features and second areas with even-numbered features on the substrate. Next, a first mask with a first pattern and a second mask with a second pattern are generated corresponding to results of design rule identification by the computing system.

Abstract translation: 提供了布局分解方法和制造应用其的半导体器件的方法。 根据布局分解方法，计算系统的逻辑处理器接收到设计布局。 然后由逻辑处理器识别布局分解的设计规则，包括识别衬底上松散区域（具有松散分布特征的区域）和密集区域（具有密集分布特征的区域），以及识别具有奇数特征的第一区域，以及 在基板上具有偶数特征的第二区域。 接下来，对应于计算系统的设计规则识别的结果，产生具有第一图案的第一掩模和具有第二图案的第二掩模。