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    METHOD OF FABRICATING ELECTRONIC CHIP
    283.
    发明申请
    METHOD OF FABRICATING ELECTRONIC CHIP 有权

    公开(公告)号：US20230068222A1

    公开(公告)日：2023-03-02

    申请号：US17896707

    申请日：2022-08-26

    Applicant: STMICROELECTRONICS (TOURS) SAS

    Inventor： Olivier ORY ,  Michael DE CRUZ

    IPC: H01L23/31 ,  H01L23/00

    Abstract: The present disclosure relates to a method for manufacturing electronic chips comprising, in order: a. forming metal contacts on the side of a first face of a semiconductor substrate, in and on which a plurality of integrated circuits have been previously formed; b. depositing a first protective resin on the metal contacts and the first face of the semiconductor substrate; c. forming first trenches of a first width on the side of a second face of the semiconductor substrate; d. depositing a second protective resin in the first trenches and on the second face of the semiconductor substrate; e. forming second trenches of a second width, less than the first width, opposite the first trenches up to the metal contacts; and f. forming third trenches opposite the second trenches, the third trenches extending through the metal contacts.

    Electronic device including interposer substrate carrying mica substrate with battery layer environmentally sealed thereto
    285.
    发明授权
    Electronic device including interposer substrate carrying mica substrate with battery layer environmentally sealed thereto 有权

    公开(公告)号：US11575172B2

    公开(公告)日：2023-02-07

    申请号：US17569016

    申请日：2022-01-05

    Applicant: STMicroelectronics (Tours) SAS

    Inventor： Vincent Jarry

    IPC: H01M50/116 ,  H01M50/124 ,  H01M6/40 ,  H01M50/10 ,  H01M10/04 ,  H01M50/528 ,  H01M50/543

    Abstract: An electronic device includes a base substrate with a mica substrate thereon. A top face of the mica substrate has a surface area smaller than a surface area of a top face of the base substrate. An active battery layer is on the mica substrate and has a top face with a surface area smaller than a surface area of a top face of the mica substrate. An adhesive layer is over the active battery layer, mica substrate, and base substrate. An aluminum film layer is over the adhesive layer, and an insulating polyethylene terephthalate (PET) layer is over the aluminum film layer. A battery pad is on the mica substrate adjacent the active battery layer, and a conductive via extends to the battery pad. A conductive pad is connected to the conductive via. The adhesive, aluminum film, and PET have a hole defined therein exposing the conductive pad.

    RECTIFIER BRIDGE
    286.
    发明申请
    RECTIFIER BRIDGE 有权

    公开(公告)号：US20220393608A1

    公开(公告)日：2022-12-08

    申请号：US17888686

    申请日：2022-08-16

    Applicant: STMicroelectronics (Tours) SAS

    Inventor： Yannick HAGUE ,  Romain LAUNOIS

    IPC: H02M7/162 ,  H02M1/00

    Abstract: A circuit includes two input nodes and two output nodes. A rectifier bridge is coupled to the input and output nodes. The rectifier bridge includes a first and second thyristors and a third thyristor coupled in series with a resistor in series. The series coupled third thyristor and resistor are coupled in parallel with one of the first and second thyristors. The first and second thyristors are controlled off, with the third thyristor controlled on, during start up with resistor functioning as an in in-rush current limiter circuit. In normal rectifying operation mode, the first and second thyristors are controlled on, with the third thyristor controlled off.

    UNIDIRECTIONAL TRANSIENT VOLTAGE SUPPRESSION DEVICE
    288.
    发明申请
    UNIDIRECTIONAL TRANSIENT VOLTAGE SUPPRESSION DEVICE 有权

    公开(公告)号：US20220360072A1

    公开(公告)日：2022-11-10

    申请号：US17661352

    申请日：2022-04-29

    Applicant: STMicroelectronics (Tours) SAS

    Inventor： Jean-Michel Simonnet ,  David Jouve ,  Frédéric Lanois

    IPC: H02H9/04 ,  H02H9/00 ,  H01L27/02

    Abstract: The present disclosure relates to a transient voltage suppression device comprising a single crystal semiconductor substrate doped with a first conductivity type comprising first and second opposing surfaces, a semiconductor region doped with a second conductivity type opposite to the first conductivity type extending into the substrate from the first surface, a first electrically conductive electrode on the first side contacting the semiconductor region and a second electrically conductive electrode on the second side contacting the substrate, a first interface between the substrate and the semiconductor region forming the junction of a TVS diode and a second interface between the first electrically conductive electrode and the semiconductor region or between the substrate and the second electrically conductive electrode forming the junction of a Schottky diode.

    METHOD FOR MANUFACTURING ELECTRONIC CHIPS
    289.
    发明申请
    METHOD FOR MANUFACTURING ELECTRONIC CHIPS 有权

    公开(公告)号：US20220344303A1

    公开(公告)日：2022-10-27

    申请号：US17811560

    申请日：2022-07-08

    Applicant: STMICROELECTRONICS (TOURS) SAS

    Inventor： Ludovic FALLOURD ,  Christophe SERRE

    IPC: H01L23/00 ,  H01L21/78

    Abstract: A method for manufacturing electronic chips includes depositing, on a side of an upper face of a semiconductor substrate, in and on which a plurality of integrated circuits has been formed, a protective resin. The method includes forming, in the protective resin, at least one cavity per integrated circuit, in contact with an upper face of the integrated circuit. Metal connection pillars are formed by filling the cavities with metal. The integrated circuits are separated into individual chips by cutting the protective resin along cut lines extending between the metal connection pillars.

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