INTEGRATED CIRCUIT COMPRISING A THREE-DIMENSIONAL CAPACITOR

    公开(公告)号:US20220271030A1

    公开(公告)日:2022-08-25

    申请号:US17741900

    申请日:2022-05-11

    IPC分类号: H01L27/08 H01L27/06 H01L49/02

    摘要: The present disclosure concerns an integrated circuit comprising a substrate, the substrate comprising a first region having a first thickness and a second region having a second thickness smaller than the first thickness, the circuit comprising a three-dimensional capacitor formed inside and on top of the first region, and at least first and second connection terminals formed on the second region, the first and second connection terminals being respectively connected to first and second electrodes of the three-dimensional capacitor.

    CAVITY FORMING METHOD
    2.
    发明公开

    公开(公告)号:US20230215733A1

    公开(公告)日:2023-07-06

    申请号:US18148329

    申请日:2022-12-29

    IPC分类号: H01L21/308 H01L21/306

    CPC分类号: H01L21/3086 H01L21/30604

    摘要: The present description concerns a method of forming a cavity in a substrate comprising: the forming of an etch mask comprising, opposite the location of the cavity, a plurality of sets of openings, the ratio between the openings and the mask of each set being selected according to the desired profile of the cavity opposite the surface of the mask having the set inscribed therein; and the wet etching of the substrate through the openings.

    CAPACITOR MANUFACTURING METHOD
    3.
    发明申请

    公开(公告)号:US20220190103A1

    公开(公告)日:2022-06-16

    申请号:US17542170

    申请日:2021-12-03

    IPC分类号: H01L49/02

    摘要: The present description concerns a capacitor manufacturing method, including the successive steps of: a) forming a stack including, in the order from the upper surface of a substrate, a first conductive layer made of aluminum or an aluminum-based alloy, a first electrode, a first dielectric layer, and a second electrode; b) etching, by chemical plasma etching, an upper portion of the stack, said chemical plasma etching being interrupted before the upper surface of the first conductive layer; and c) etching, by physical plasma etching, a lower portion of the stack, said physical plasma etching being interrupted on the upper surface of the first conductive layer.

    BATTERY WITH FRONT FACE AND REAR FACE CONTACTS

    公开(公告)号:US20200091470A1

    公开(公告)日:2020-03-19

    申请号:US16692367

    申请日:2019-11-22

    摘要: A battery structure has structure anode and cathode contacts on a front face and on a rear face. The battery structure includes a battery having battery anode and cathode contacts only on a front face thereof. A film including a conductive layer and an insulating layer jackets the battery. The conductive layer extends over the battery anode and cathode contacts and is interrupted therebetween. Openings are provided in the insulating layer on the front and rear faces of the battery structure to form the structure anode and cathode contacts of the battery structure.

    MICROBATTERY ASSEMBLY
    9.
    发明申请

    公开(公告)号:US20220311078A1

    公开(公告)日:2022-09-29

    申请号:US17839196

    申请日:2022-06-13

    摘要: The disclosure relates to microbattery devices and assemblies. In an embodiment, a device includes a plurality of microbatteries, a first flexible encapsulation film, and a second flexible encapsulation film. Each of the microbatteries includes a first contact terminal and a second contact terminal spaced apart from one another. The first flexible encapsulation film includes a first conductive layer electrically coupled to the first contact terminal of each of the microbatteries, and a first insulating layer on the first conductive layer. The second flexible encapsulation film includes a second conductive layer electrically coupled to the second contact terminal of each of the microbatteries, and a second insulating layer on the second conductive layer.

    INTEGRATED CIRCUIT COMPRISING A THREE-DIMENSIONAL CAPACITOR

    公开(公告)号:US20200286886A1

    公开(公告)日:2020-09-10

    申请号:US16801038

    申请日:2020-02-25

    IPC分类号: H01L27/08 H01L49/02 H01L27/06

    摘要: The present disclosure concerns an integrated circuit comprising a substrate, the substrate comprising a first region having a first thickness and a second region having a second thickness smaller than the first thickness, the circuit comprising a three-dimensional capacitor formed inside and on top of the first region, and at least first and second connection terminals formed on the second region, the first and second connection terminals being respectively connected to first and second electrodes of the three-dimensional capacitor.