公开(公告)号：US20230230906A1

公开(公告)日：2023-07-20

申请号：US18154638

申请日：2023-01-13

Applicant: STMICROELECTRONICS (TOURS) SAS

Inventor： Nicolas MODE ,  Ludovic FALLOURD ,  Laurent BARREAU

IPC: H01L23/498 ,  H01L23/29 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56

CPC classification number: H01L23/49805 ,  H01L23/49838 ,  H01L23/293 ,  H01L23/3135 ,  H01L21/486 ,  H01L21/565

Abstract: The present disclosure concerns a method of manufacturing an electronic component and the obtained component, comprising a substrate, comprising the successive steps of: depositing a first layer of a first resin activated by abrasion to become electrically conductive, on a first surface of said substrate comprising at least one electric contact and, at least partially, on the lateral flanks of said substrate; partially abrading said first layer on the flanks of said substrate.

公开(公告)号：US20210175204A1

公开(公告)日：2021-06-10

申请号：US17111198

申请日：2020-12-03

Applicant: STMicroelectronics (Tours) SAS

Inventor： Ludovic FALLOURD ,  Christophe SERRE

IPC: H01L23/00 ,  H01L21/78

Abstract: A method for manufacturing electronic chips includes depositing, on a side of an upper face of a semiconductor substrate, in and on which a plurality of integrated circuits has been formed, a protective resin. The method includes forming, in the protective resin, at least one cavity per integrated circuit, in contact with an upper face of the integrated circuit. Metal connection pillars are formed by filling the cavities with metal. The integrated circuits are separated into individual chips by cutting the protective resin along cut lines extending between the metal connection pillars.

公开(公告)号：US20210175203A1

公开(公告)日：2021-06-10

申请号：US17110063

申请日：2020-12-02

Applicant: STMicroelectronics (Tours) SAS

Inventor： Ludovic FALLOURD ,  Christophe SERRE

IPC: H01L23/00 ,  H01L21/78

Abstract: A method for manufacturing electronic chips includes forming, on a side of an upper face of a semiconductor substrate, in and on which a plurality of integrated circuits has been formed, trenches laterally separating the integrated circuits. At least one metal connection pillar per integrated circuit is deposited on the side of the upper face of the substrate, and a protective resin extends in the trenches and on an upper face of the integrated circuits. The method further includes forming, from an upper face of the protective resin, openings located across from the trenches and extending over a width greater than or equal to that of the trenches, so as to clear a flank of at least one metal pillar of each integrated circuit. The integrated circuits are separated into individual chips by cutting.

公开(公告)号：US20190252649A1

公开(公告)日：2019-08-15

申请号：US16270282

申请日：2019-02-07

Applicant: STMICROELECTRONICS (TOURS) SAS

Inventor： Ludovic FALLOURD

IPC: H01M2/02

CPC classification number: H01M2/0267 ,  H01M2/0207 ,  H01M2/026 ,  H01M2/0275 ,  H01M2/0287 ,  H01M2/029 ,  H01M2/1066 ,  H01M6/40 ,  H01M10/0436 ,  H01M10/052 ,  H01M10/0585 ,  H01M2220/30

Abstract: The disclosure concerns a battery assembly including two batteries having their active layers facing each other and sharing an encapsulation layer.

公开(公告)号：US20220344303A1

公开(公告)日：2022-10-27

申请号：US17811560

申请日：2022-07-08

Applicant: STMICROELECTRONICS (TOURS) SAS

Inventor： Ludovic FALLOURD ,  Christophe SERRE

IPC: H01L23/00 ,  H01L21/78

Abstract: A method for manufacturing electronic chips includes depositing, on a side of an upper face of a semiconductor substrate, in and on which a plurality of integrated circuits has been formed, a protective resin. The method includes forming, in the protective resin, at least one cavity per integrated circuit, in contact with an upper face of the integrated circuit. Metal connection pillars are formed by filling the cavities with metal. The integrated circuits are separated into individual chips by cutting the protective resin along cut lines extending between the metal connection pillars.

公开(公告)号：US20210151347A1

公开(公告)日：2021-05-20

申请号：US16950787

申请日：2020-11-17

Applicant: STMicroelectronics (Tours) SAS

Inventor： Ludovic FALLOURD

IPC: H01L21/762 ,  H01L21/56 ,  H01L21/02

Abstract: The present disclosure relates to a method for manufacturing electronic chips. The method includes forming a plurality of trenches on a first face of a semiconductor substrate, in and on which a plurality of integrated circuits has been formed. The trenches delimit laterally a plurality of chips, and each of the chips includes a single integrated circuit. The method further includes electrically isolating flanks of each of the chips by forming an electrically isolating layer on lateral walls of the trenches.